About L2 ECC setting in AM335x.

RY,

I thinks is always enabled. 

RY, you should be able to find this in the Cortex-A8 documentation on the ARM website www.arm.com

Regards,

James

I believe L2 ECC is disabled by default on the Cortex A8. You can optionally enable parity OR ECC by writing the L2 CACR (cache access control register). For more details take a look at the Cortex A8 TRM.

Hello.

Thank you very much for your every answers.
I have read L2 CACR register. And I have been able to see that the ECC is disabled after reset.

Since I have not been able to write to enable ECC on L2 CACR register, I think that the L2 ECC is not available on AM335x.

Is it right?

Best regards,
RY

Hi,RY9983

I have the same question,can not write to the L2 CACR,do you enable L2 ECC successed by now?

Thanks

YanTCK

Hello, Y tck.

Yes. I have been able to enable L2 ECC.

It will be updated on TRM in the future.
And, there is a same method to access L2 cache auxiliary control register for enabling L2 ECC.
You can see it on TRM of OMAP3530(spruf98x : P3409).

Best regards,
RY

Y tck.

Sorry, the TRM habe been already updated.
You should check 3.1.4.2.2 (spruh73g: P167).

Best regards,
RY

Hi,RY

Thank for your reply,but I can not find 3.1.4.2.2 in the TRM of OMAP3530.

YanTCK

Hi,RY

I got it ,it is the TRM of AM335x(p167).

thank you!

YanTCK