KITL over DM9000 ethernet controller hangs ...

The reference BSP from TI does not support the DM9000 ethernet controller, it has most likely been developped by the people in charge of the BSP provided by Embest. I suggest you turn to them for support on this particular feature.

Well...

I already did contact them, butthe Embest support team does not reply as quick as the Adeneo support team ;o) ...

C est la vie

Franck,

I'm not sure whether its supported, but still have you checked for VMINI support for USB-Fn driver? Also have you disabled USB Function driver in catalog and tried the same?

Hi Thomas,

I am trying to contact Embest diretly to get an eventual Beta version of the DM9000 driver for KITL,.

Since you seem to be experienced on these matters, Mayb you can give me another way to achieve what I want.

I can doenload and debug using KITL over USBRNDIS, no problems.

I can download hrough DM9000, but I cannot use KITL over DM9000. However, EBoot and KITL use the same DM9000 driver ! it must be the way KITL initialise the DM9000 driver, bu I di not find it yet...

If you support a different type of ethernet controller, maybe you also have EBoot and KITL using the same driver ? is there any particular way to read memory / st registers that I could reproduce ? I mean, if I could not do anyting over DM9000, OK, the driver is faulty.

But if th EBoot booloader can download the NK.bin firmware, chances are KITL can also run over this driver... I will keep investigating...

Lets take te problem the opposite way: in order to develop and debug my custpm USB FN driver, I use a tst pogram tha first switch the USBFN profile featured by the DevKit8500: This consists of a DevicIoControl using a handle on the USBFN kernel driver.

How can I access this USBFN kernel driver if KITL is using USBFN RNDIS drivr?

I cannot believe I am the first developpr to add a USB FN profile in the kernel ?

thanks for your advice

Cheers

Franck

Franck,

I'm not in touch with WINCE from past 3 years. I'm trying recollect from my memory, so I may not be specific in my response.

I believe KITL over USBFN is a very slow and certainly not a good way of using KITL, especially when you have an Ethernet controller available. 

In fact DM9000 is one of the most simplest Ethernet controller, which is there from so long. 

Can you enable more DEBUGMSG and share the complete serial logs when you are booting with KITL through DM9000? 

>> I'm not in touch with WINCE from past 3 years

lucky you ! ;o)

I will send you a detailed log with all messages allowed.

But in short:

Eboot calls the DM9000 driver,

reads correct MC address, and move on from there, with DHCP request and so on...

KITL calls the DM9000 driver, but reads a MAC 0:0:0:0:0:0m then hangs

If I allow INTR message, it looks like the INterrupt engine is in an endless loop, a bit like an intrrupt conflict with another kernel driver.

If you say the DM9000 has ben there for a long time, and you guys supported the LN9XXX (correct?) controller, then I MUST be able to get this working.

Ill be back @ office on thursday, and I ll send you a full detailed log

Thanks for your support

Franck

Franck,

I like WINCE more than Linux :) I feel that Microsoft has made a wonderful code base for WINCE, well thought and designed.

Can you try the following?

1. EBoot command prompt, see whether you can enter the network info, including mac id? 

2. Try configuring KITL network for static IP and enter a static IP.

3. Enable KITL in polled mode rather than interrupt mode. There might be a command line option for the same.

4. If these steps are not successful, hard code a mac id after it reads 0:0:0:0:0:0 and see whether it proceeds further.

Hi Renjith,

I have tried te different steps you suggest:

- 1: I can set static IP and DHCP option, but I canno set the MAC @, as I get errrmsg:  "Set Ethernet (LAN9xxx) MAC Address: Invalid Ethernet chip ID (0x0)!"

So I guess EBoot.nb0 calls LAN9xxx driver iostaed of DM9000... I might be able to fix this ...

- 2 : OK, I have done that, no change...

- 3 KITL in polling mode =same result ...

- 4 Hardcoded MAC Address: still hag at the same time...

Whattricks me out is the following behaviour:

EBoot and KITL both call the same method DM9000DBG_Init in d9000a.c file.

The way they read te registers is the same, using data index and data value. When EBoot goes al the way to downlod with success, KITL hangs when tying to read the registers, starting wth VID/PID:

dm9000a.c file, line 193:

// Get DM9000A VID/PID

//--------------------

DM9000_PINDEX = DM9_PIDH;

ID = ( DM9000_PDATA & 0xff ) << 8;

DM9000_PINDEX = DM9_PIDL;

ID += ( DM9000_PDATA & 0xff );

ID = ID << 16;

DM9000_PINDEX = DM9_VIDH;

ID += ( DM9000_PDATA & 0xff ) << 8;

DM9000_PINDEX = DM9_VIDL;

ID += ( DM9000_PDATA & 0xff );

THis is where KITL hangs... I have readin apost one sould define a register structure like in the LAN9xxx driver:

typedef

struct

{

    UINT32 rx_fifo;            

// 0x00

    UINT32 rx_fifo_alias[7];   

// 0x04

    UINT32 tx_fifo;            

// 0x20

    UINT32 tx_fifo_alias[7];   

// 0x24

    UINT32 rx_status_fifo;     

// 0x40

    UINT32 rx_status_fifo_peek;

// 0x44

    UINT32 tx_status_fifo;     

// 0x48

    UINT32 tx_status_fifo_peek;

// 0x4c

    UINT32 id_rev;             

// 0x50

    UINT32 irq_cfg;            

// 0x54

    UINT32 int_sts;            

// 0x58

    UINT32 int_en;             

// 0x5c

    UINT32 reserved0;          

// 0x60

    UINT32 byte_test;          

// 0x64

    UINT32 fifo_int;           

// 0x68

    UINT32 rx_cfg;             

// 0x6c

    UINT32 tx_cfg;             

// 0x70

    UINT32 hw_cfg;             

// 0x74

    UINT32 rx_dp_ctrl;         

// 0x78

    UINT32 rx_fifo_inf;        

// 0x7c

    UINT32 tx_fifo_inf;        

// 0x80

    UINT32 pmt_ctrl;           

// 0x84

    UINT32 gpio_cfg;           

// 0x88

    UINT32 gpt_cfg;            

// 0x8c

    UINT32 gpt_cnt;            

// 0x90

    UINT32 reserved1;          

// 0x94

    UINT32 endian;             

// 0x98

    UINT32 free_run;           

// 0x9c

    UINT32 rx_drop;            

// 0xa0

    UINT32 mac_csr_cmd;        

// 0xa4

    UINT32 mac_csr_data;       

// 0xa8

    UINT32 afc_cfg;            

// 0xac

    UINT32 e2p_cmd;            

// 0xb0

    UINT32 e2p_data;           

// 0xb4

} LAN911X_REGS;

, instead of a list of enum addresses like in dm9000:

typedef

enum {

DM9_NCR = 0,

DM9_NSR,

DM9_TXCR,

DM9_TXSR1,

DM9_TXSR2,

DM9_RXCR,

DM9_RXSR,

DM9_ROCR,

DM9_BACKTH,

DM9_PAUSETH,

DM9_FLOW,

DM9_EPCNTL,

/* 0x0B */

DM9_EPADDR,

DM9_EPLOW,

DM9_EPHIGH,

DM9_WCR,

DM9_PAR0 = 0x10,

DM9_PAR1,

DM9_PAR2,

DM9_PAR3,

DM9_PAR4,

DM9_PAR5,

DM9_MAR0 = 0x16,

DM9_MAR1,

DM9_MAR2,

DM9_MAR3,

DM9_MAR4,

DM9_MAR5,

DM9_MAR6,

DM9_MAR7,

DM9_GPCR = 0x1E,

DM9_GPR,

DM9_TRAL = 0x22,

DM9_TRAH = 0x23,

DM9_RWAL = 0x24,

DM9_RWAH = 0x25,

DM9_VIDL = 0x28,

DM9_VIDH,

DM9_PIDL,

DM9_PIDH,

DM9_CHIPREV = 0x2C,

DM9_TCR2 = 0x2D,

DM9_OCR,

DM9_SMCR,

DM9_EXTCSR,

DM9_TCSCR,

DM9_RCSCSR,

DM9_MRCMDX = 0xF0,

DM9_MRCMDX1,

DM9_MRCMD = 0xF2,

DM9_MDRAH = 0xF4,

DM9_MDRAL,

DM9_MWCMDX = 0xF6,

DM9_MWCMD = 0xF8,

DM9_MDWAL = 0xFA,

DM9_MDWAH = 0xFB,

DM9_TXLENL = 0xFC,

DM9_TXLENH,

DM9_ISR = 0xFE,

DM9_IMR

} DM9000_REGISTER_TYPE;

OK, fine, I can admit that, but why Eboot can read regisers this way and not KITL...

If you have any advice regarding how to accss prperly registers in an ethernet controller, I d love to read them ...

Franck,

There are couple of things here that stops your driver from reading the registers properly.

1. The registers are mapped to the GPMC address space by configuring the GPMC controller registers.

2. Check whether the GPMC registers GPMC_CONFIG1-7 for your chip select is configured same as EBOOT. 

3. Then check whether the base address used is same as in EBOOT?

4. If the base address is proper, in case of KITL, the address has to be translated to a virtual address. This should be done using OALPAToVA API. 

5. Check the base address used during the register access and print the address and share with me.

Hi Renjith,

Thanks for tha great help, it certainly makes things move on:

- The GPMC address spce was not initialised by the GPMC driver similarly to the bootloader.

- th base adress is the same when calledby the bootloader and KITL:

0x15000000

But the register access is done at that same address, no shift to a virtual address space using "OALPAtoVA"

I will try that and let you know if I can read some MAC Address and launch KITL over DM9000...

Thanks again for your precious help

Franck

Franck,

Did you check the GPMC register values in kernel, and whether its same as EBOOT? If its different, even having the same value 0x15000000 will not help. 

If OALPAtoVA/OALPAtoUA is not happening, then anyway its not going to work. 

Hi Renjith,

First of all, thanks to your advie and knowledge, I must admit I have a clearer view on the DevKit8500 HW level andkrnel arcitcture...

But wth all these great advice, it still hags when KITL triesto connect through the DM9000 ...

I hve added the shif from Physical to Virtual address:

EBoot uses 0x15000000, whereas KITL uses 0xfe00fe afte 0x1500000 was passed to OALPAtoVA

Even withthis address, it still reads a MAC @ 0:0:0:0:0:0

So I have hardcoded the MAC address to f4:6f:e1:87:90:ff

  I have also set KITL in polling mode, and added extra levels of log.

 The latst result is there: you ca see both Eboot download and KITL attempt to start:

DM9000DBG_Init: called from EBoot: DevKit8500 v1.1.2, MAC @ 0x87EFFF74 DM9000DBG_Init: IndexPort = 0x15000000 , DataPort = 0x15000000 DM9000 Mac Address: f4:6f:e1:87:90:ff DM3730 Found DM9000 ID:90000a46 DM9000 Chip Revison: 0x19 DM9000_Reset... DM9000 Work in 16 Bus Width DM9000 Mac : f4 DM9000 Mac : 6f DM9000 Mac : e1 DM9000 Mac : 87 DM9000 Mac : 90 DM9000 Mac : ff Link on ethernet at:100 Mbps DM9000_Init OK. INFO: Boot device uses MAC f4:6f:e1:87:90:ff INFO: *** Device Name EVM3730-37119 *** InitDHCP():: Calling ProcessDHCP() ProcessDHCP()::DHCP_INIT Got Response from DHCP server, IP address: 172.29.12.32

ProcessDHCP()::DHCP IP Address Resolved as 172.29.12.32, netmask: 255.255.248.0 Lease time: 432000 seconds Got Response from DHCP server, IP address: 172.29.12.32 No ARP response in 2 seconds, assuming ownership of 172.29.12.32 +EbootSendBootmeAndWaitForTftp Sent BOOTME to 255.255.255.255 Packet has the following data:   boot.bin[NULL]octet[NULL] TFTP packet could have 1 name/value pairs Locked Down Link 1 Src IP 172.29.12.32 Port 03D4   Dest IP 172.29.12.11 Port F9D1 Default TFTP block size set to: 512 bytes There were no options detected in the TFTP EthDown::TFTPD_OPEN::boot.bin -EbootSendBootmeAndWaitForTftp

BL_IMAGE_TYPE_BIN

Download file information: ----------------------------------------------------------- [0]: Address=0x80101000  Length=0x01fb8348  Save=0x80001000 ----------------------------------------------------------- Download file type: 1 TFTP: Desktop losing ACK, block number = 29636, Ack again rom_offset=0x0. ImageStart = 0x80101000, ImageLength = 0x1FB8348, LaunchAddr = 0x8010F904

Completed file(s): ------------------------------------------------------------------------------- [0]: Address=0x80101000  Length=0x1FB8348  Name="" Target=RAM ROMHDR at Address 80101044h Got EDBG_CMD_JUMPIMG Got EDBG_CMD_CONFIG, flags:0x00000000 Launch Windows CE image by jumping to 0x8000f904...

Windows CE Kernel for ARM (Thumb Enabled) Built on Jan 25 2012 at 17:30:19 +OEMInit INFO:OALLogSetZones: dpCurSettings.ulZoneMask: 0xd00f OAL: CPU revision 0xffffffff OAL: CPU L2 Aux register 0x400042 CPU CP15 Control Register = 0xc5387f CPU CP15 Auxiliary Control Register = 0x100e3 +OALPowerInit()  Disable serial debug messages during PRCM DeviceInitialize  Serial debug messages renabled -OALPowerInit() +OALInterruptInit OMAP35XX_TPS659XX_TI_V1 +OEMInterruptMapInit -OEMInterruptMapInit +OALIntrRequestSysIntr(1, 0x881074bc, 0x00000004) -OALIntrRequestSysIntr(sysIntr = 16) +OEMInterruptEnable(16, 0x0, 0) +OALTranslateSysIntr(16) -OALTranslateSysIntr(rc = 1) +OALntrEnableIrqs(5, 0x8810d580) -OALIntrEnableIrqs(rc = 1) -OEMInterruptEnable(rc = 1) -OALInterruptInit(rc = 1) +PrcmDeviceEnableFClock(devId=36, 1) +_PrcmDeviceHwUpdateAutoidle(devId=36) -_PrcmDeviceHwUpdateAutoidle()=1  PrcmDeviceEnableFClock skip update clocks -PrcmDeviceEnableFClock()=1 +PrcmDeviceEnableIClock(devId=36, 1)  PrcmDeviceEnableIClock skip update clocks -PrcmDeviceEnableIClock()=1 +OALIntrRequestSysIntr(1, 0x881074b8, 0x00000004) -OALIntrRequestSysIntr(sysIntr = 17) +OEMInterruptEnable(17, 0x0, 0) +OALTranslateSysIntr(17) -OALTranslateSysIntr(rc = 1) +OALntrEnableIrqs(5, 0x8810d594) -OALIntrEnableIrqs(rc = 1) -OEMInterruptEnable(rc = 1) +OALSRAMFnInit() -OALSRAMFnInit() --- High Performance Frequecy is 32768 khz--- +OALKitlInit(' s', 0x 8x - -2146270020/61/0x 8x, 0x 8x)

DeviceId................. EVM3730-

pArgs->flags............. 0x3D

pArgs->devLoc.IfcType.... 0

pArgs->devLoc.LogicalLoc. 0x15000000

pArgs->devLoc.PhysicalLoc 0x0

pArgs->devLoc.Pin........ -2015349248

pArgs->ip4address........ 0

pDevice->Name............  s

pDevice->ifcType......... 0

pDevice->id.............. 0x480AB000

pDevice->resource........ 0

pDevice->type............ 2

pDevice->pDriver......... 0x8811102C

+OEMIoControl(0x1010014, 0xffffc6bc, 40, 0x0, 0, 0x0) -OEMIoControl(rc = 1) DM9000DBG_Init: called from NK.bin: DevKit8500 v1.1.8, static MAC DM9000DBG_Init: IndexPort = 0xfe00fe , DataPort = 0xfe04fe DM9000 Mac Address: f4:6f:e1:87:90:ff OEMInterruptHandler(Irq 37) +OALIntrDoneIrqs(1, 0xffffc500) -OALIntrDoneIrqs OEMInterruptHandler(Irq 37) +OALIntrDoneIrqs(1, 0xffffc500) -OALIntrDoneIrqs OEMInterruptHandler(Irq 37) +OALIntrDoneIrqs(1, 0xffffc500) -OALIntrDoneIrqs OEMInterruptHandler(Irq 37) +OALIntrDoneIrqs(1, 0xffffc500) -OALIntrDoneIrqs...

and so on... it remans locked in the same loop  OEMInterruptHandler(Irq 37) +OALIntrDoneIrqs(1, 0xffffc500) -OALIntrDoneIrqs

the lst thing I will try is to se the second argument of

OALPAtoVA(IndexPortAddress, TRUE);

to FALSE instead

Is there any tip to see whether this virtual address is the one assotaed with the LAN controller ?

Thanks again for your time

Franck

Franck,

First of all the Virtual address 0x00fe_00fe is not a valid kernel address. It should be in the range of 0x8000_0000 to 0xFFFF_FFFF. So we need to see why it fail. I don't remember the path correctly, but the static memory map is defined in a file called oemaddrtab.inc in one of the include directories of your BSP. Search for that and see whether any definition exists for the address 0x1500_0000? Please attach that file in your reply. 

Regd. interrupts: Can you disable KITL interrupt mode and enable only polling mode always and see whether any difference is there or not?

If its already disabled, then there is a chance that this could be timer interrupts. That we can debug later. 

Hi Renjith,

I fully understand your point, I also expected the virtual address to be past 0x8000 0000 ...

I had a look at the aforementionned file: oemaddrtab_cfg.inc

I found one ! but not for the platform I am using ... ;o) There is such a file for MAINSTONEIII and DEVICEEMULATOR platforms, but not for my DevKit8500 ...

I guess this the starting point of my DM9000 ethernet driver for KITL ?...

Regarding interrupts, the log I sent you was with KITL in POLLING mode, so the interrupt conflict (if there is any) does not come from KITL ...

Looking forward reading from you regarding virtual memory for LN controllers.

Cheer

Franck

Frack,

Search for all the .inc files in your BSP code. The name might be different like addrtab.inc or something like that. The file has to be present in your BSP. Send me the file, we can sort out the issues. 

I think the interrupts are from timer if not Ethernet. 

Hi Renjith,

I found "addrtab_cfg.inc" which seems to be our file.

They mention config.bib fr the memory map, so I also copied the content of my cnfig.bib file

##################################   addrtab_cfg.inc  ################################

; Copyright (c) 2007, 2008 BSQUARE Corporation. All rights reserved.

;

;==============================================================================

;             Texas Instruments OMAP(TM) Platform Software

; (c) Copyright Texas Instruments, Incorporated. All Rights Reserved.

;

; Use of this software is controlled by the terms and conditions found

; in the license agreement under which this software has been supplied.

;

;==============================================================================

;

;------------------------------------------------------------------------------

;

;  File:  memory_cfg.inc

;

;  This file is used to define g_oalAddressTable. This table is passed to

;  KernelStart to estabilish physical to virtual memory mapping. This table

;  is used also in memory OAL module to map between physical and virtual

;  memory addresses via OALPAtoVA/OALVAtoPA functions.

;

;  The config.bib file defines image memory layout ant it contains virtual

;  cached memory addresses which must be synchronized with g_oalAddressTable.

;  With each table change make sure that those constant are still valid.

;

;------------------------------------------------------------------------------

;  Export Definition

        EXPORT  g_oalAddressTable[DATA]

;------------------------------------------------------------------------------

;  Table format: cached address, physical address, size

g_oalAddressTable

IF BSP_SDRAM_BANK1_ENABLE <> 1

        DCD     0x84000000, 0x80000000, 128     ; SDRAM

        DCD     0x8C000000, 0x0C000000,  16     ; CS0, OneNand/Nand flash

        DCD     0x8D000000, 0x15000000,  16     ; CS5, LAN9115

        DCD     0x91000000, 0x48000000,  16     ; L4 Core/Wakeup registers

        DCD     0x92000000, 0x49000000,   1     ; L4 Peripheral

        DCD     0x93000000, 0x68000000,  16     ; L3 registers

        DCD     0x94000000, 0x6C000000,  16     ; SMS registers

        DCD     0x95000000, 0x6D000000,  16     ; SDRC registers

        DCD     0x96000000, 0x6E000000,  16     ; GPMC registers

        DCD     0x97000000, 0x40200000,   1     ; 62KB SRAM

        DCD     0x98000000, 0x5C000000,  16     ; L3 interconnect

        DCD     0x99000000, 0x00000000,   1     ; ROM

        DCD     0x00000000, 0x00000000,   0     ; end of table

ELSE

        DCD     0x80100000, 0x80000000, 256     ;; SDRAM

        DCD     0x90100000, 0x90000000, 211     ; SDRAM

        DCD     0x9f800000, 0x0C000000,   1     ; CS0, OneNand/Nand flash

        DCD     0x9f900000, 0x15000000,   1     ; CS5, LAN9115

        DCD     0x9fa00000, 0x48000000,   4     ; L4 Core/Wakeup registers

        DCD     0x9fe00000, 0x49000000,   1     ; L4 Peripheral

        DCD     0x9ff00000, 0x68000000,   1     ; L3 registers

        DCD     0x9d400000, 0x6C000000,   1     ; SMS registers

        DCD     0x9d500000, 0x6D000000,   1     ; SDRC registers

        DCD     0x9d600000, 0x6E000000,  16     ; GPMC registers

        DCD     0x9e600000, 0x40200000,   1     ; 62KB SRAM

        DCD     0x9e700000, 0x5C000000,  16     ; L3 interconnect

        DCD     0x9f700000, 0x00000000,   1     ; ROM

        DCD     0x00000000, 0x00000000,   0     ; end of table

  ENDIF

;------------------------------------------------------------------------------

END

##################################   config.bib ################################

 Copyright (c) 2007, 2008 BSQUARE Corporation. All rights reserved. ; ;               Texas Instruments OMAP(TM) Platform Software ; (c) Copyright Texas Instruments, Incorporated. All Rights Reserved. ; ; ;   Use of this software is controlled by the terms and conditions found ;   in the license agreement under which this software has been supplied. ; ;------------------------------------------------------------------------------- ;    MEMORY ;   Name                        VA          Length      Type     ARGS                        80100000    00001000    RESERVED ; 4K #if (defined BSP_DSPLINK || defined BSP_TI_DVSDK) IF BSP_SDRAM_BANK1_ENABLE     NK                          80101000    047FF000    RAMIMAGE ; 72MB - 4K     DISPLAY                     84900000    01000000    RESERVED ; 16MB     CMEM_DSP                    85900000    02800000    RESERVED ; 40 MB     RAM                         88100000    15300000    RAM      ; 128+211MB ELSE     NK                          84001000    01FFF000    RAMIMAGE ; 32MB - 4K     RAM                         86000000    02800000    RAM      ; 40 MB     DISPLAY                     88800000    01000000    RESERVED ; 16MB     CMEM_DSP                    89800000    02800000    RESERVED ; 40 MB ENDIF #else IF BSP_SDRAM_BANK1_ENABLE     NK                          84001000    06FFF000    RAMIMAGE ; 112MB - 4K     DISPLAY                     8B000000    01000000    RESERVED ; 16MB     RAM                         8C000000    08000000    RAM      ; 128MB ELSE     NK                          84001000    02FFF000    RAMIMAGE ; 48MB - 4K     RAM                         87000000    04000000    RAM      ; 64MB     DISPLAY                     8B000000    01000000    RESERVED ; 16MB ENDIF #endif

nk.exe:dwOEMFailPowerPaging     00000000    00000001    FIXUPVAR nk.exe:dwOEMDrWatsonSize        00000000    0004B000    FIXUPVAR nk.exe:dwOEMPRCMCLKSSetupTime   00000000    00000140    FIXUPVAR nk.exe:dwOEMMaxIdlePeriod       00000000    000003E8    FIXUPVAR nk.exe:dwOEMTargetProject       00000000    00000001    FIXUPVAR

IF _TGTPROJ=smartfon nk.exe:dwOEMTargetProject       00000000    00000002    FIXUPVAR ENDIF _TGTPROJ=smartfon

IF IMGHIGHSECURITY nk.exe:dwOEMHighSecurity        00000000    00000001    FIXUPVAR ELSE nk.exe:dwOEMHighSecurity        00000000    00000002    FIXUPVAR ENDIF

; location for context save/restore from off mode (MUST BE DDR PHYSICAL ADDR VALUE) ; nk.exe:dwOEMMPUContextRestore   00000000    80000800    FIXUPVAR

;-------------------------------------------------------------------------------

CONFIG ; @CESYSGEN IF !NK_NKNOCOMP    COMPRESSION=ON ; @CESYSGEN ENDIF !NK_NKNOCOMP ; @CESYSGEN IF NK_NKNOCOMP ; @CESYSGEN ENDIF NK_NKNOCOMP     KERNELFIXUPS=ON

IF BSP_SDRAM_BANK1_ENABLE     FSRAMPERCENT=0x80808080 ELSE #if (defined BSP_DSPLINK || defined BSP_TI_DVSDK)     FSRAMPERCENT=0x40404040 #else     FSRAMPERCENT=0x80808080 #endif ENDIF

IF BSP_SDRAM_BANK1_ENABLE     ; NK (RAMIMAGE) and RAM (RAM) areas are not contiguous, turn off AUTOSIZE     AUTOSIZE=OFF     ;always to ON by wangwj ELSE     AUTOSIZE=ON ENDIF

IF IMGPROFILER       PROFILE=ON ELSE     PROFILE=OFF ENDIF

IF IMGFLASH     ROMOFFSET=FC000000 ENDIF

; ; ROMFLAGS is a bitmask of options for the kernel ;   ROMFLAGS    0x0001      Disallow Paging ;   ROMFLAGS    0x0002      Not all KMode (not supported under CE6) ;   ROMFLAGS    0x0010      Trust Module only ; IF IMGTRUSTROMONLY     IF IMGNOTALLKMODE        ROMFLAGS=12     ELSE        ROMFLAGS=10     ENDIF ELSE     IF IMGNOTALLKMODE        ROMFLAGS=02     ELSE        ROMFLAGS=00     ENDIF ENDIF

;-------------------------------------------------------------------------------

The contentis not easy to read, butI cannot insert the files from my browser ...???...

I will try to send the files to you from a different browser

looking forward to your point of you on my memor map

Thanks

Franck

Franck,

Can you cross check what is the base address that is used to read the registers in the DM9000 driver? Looks like addrtab configuration is proper. Also can you dump the GPMC config registers in the kernel and share?

You can send me an e-mail at renjith..thomas@pathpartnertech.com, instead of pasting it.

Renjth,

I have sent you an email, but y firewall behave funny, so I am not sure ifyou got it...

this is what I sent:

Can you cross check what is the base address that is used to read the registers in the DM9000 driver? Looks like addrtab configuration is proper.

the following code is used to read the DM9000 registers:

#define DM9000_PINDEX  (*(volatile USHORT *)(dwIndexPortAddress)) #define DM9000_PDATA   (*(volatile USHORT *)(dwDataPortAddress))

static void DM9000Write(int reg, UCHAR value) {  DM9000_PINDEX = reg;  DM9000_PDATA  =  value & 0xff; }

static unsigned char DM9000Read(int reg) {  DM9000_PINDEX = reg;  return (DM9000_PDATA & 0xff); }

dwIndexPortAddress is effectively set to 0x15000000

dwDataPortAddress is set to dwIndexPortAddress + 0x400;

I am not sure why there is this offset

this is the register map I use for the DM9000:

typedef enum {  DM9_NCR = 0,  DM9_NSR,  DM9_TXCR,  DM9_TXSR1,  DM9_TXSR2,  DM9_RXCR,  DM9_RXSR,  DM9_ROCR,  DM9_BACKTH,  DM9_PAUSETH,  DM9_FLOW,  DM9_EPCNTL, /* 0x0B */  DM9_EPADDR,  DM9_EPLOW,  DM9_EPHIGH,  DM9_WCR,

 DM9_PAR0 = 0x10,  DM9_PAR1,  DM9_PAR2,  DM9_PAR3,  DM9_PAR4,  DM9_PAR5,

 DM9_MAR0 = 0x16,  DM9_MAR1,  DM9_MAR2,  DM9_MAR3,  DM9_MAR4,  DM9_MAR5,  DM9_MAR6,  DM9_MAR7,

 DM9_GPCR = 0x1E,  DM9_GPR,

 DM9_TRAL = 0x22,  DM9_TRAH = 0x23,  DM9_RWAL = 0x24,  DM9_RWAH = 0x25,    DM9_VIDL = 0x28,  DM9_VIDH,  DM9_PIDL,  DM9_PIDH,

 DM9_CHIPREV = 0x2C,    DM9_TCR2 = 0x2D,  DM9_OCR,  DM9_SMCR,  DM9_EXTCSR,  DM9_TCSCR,  DM9_RCSCSR,

 DM9_MRCMDX = 0xF0,  DM9_MRCMDX1,  DM9_MRCMD = 0xF2,  DM9_MDRAH = 0xF4,  DM9_MDRAL,  

 DM9_MWCMDX = 0xF6,  DM9_MWCMD = 0xF8,  DM9_MDWAL = 0xFA,  DM9_MDWAH = 0xFB,    DM9_TXLENL = 0xFC,  DM9_TXLENH,

 DM9_ISR = 0xFE,  DM9_IMR   } DM9000_REGISTER_TYPE;

Is there a double map, with 0x1500000 to write to registers, and 0x15000400 to read the content back ?

Also can you dump the GPMC config registers in the kernel and share?

 OMAP_GPMC_REGS* pGpmc = OALPAtoUA(OMAP_GPMC_REGS_PA);  OMAP_SDRC_REGS* pSdrc = OALPAtoUA(OMAP_SDRC_REGS_PA);  OMAP_PRCM_GLOBAL_PRM_REGS * pPrmGlobal = OALPAtoUA(OMAP_PRCM_GLOBAL_PRM_REGS_PA);  OMAP_SYSC_PADCONFS_REGS *pConfig = OALPAtoUA(OMAP_SYSC_PADCONFS_REGS_PA);

 unsigned int val = 0;  BOOL bColdBoot;

 //  Global GPMC Configuration  OUTREG32(&pGpmc->GPMC_SYSCONFIG,       0x00000008);   // No idle, L3 clock free running       OUTREG32(&pGpmc->GPMC_IRQENABLE,       0x00000000);   // All interrupts disabled     OUTREG32(&pGpmc->GPMC_TIMEOUT_CONTROL, 0x00000000);   // Time out disabled     OUTREG32(&pGpmc->GPMC_CONFIG,          0x00000011);   // WP high, force posted write for NAND   

#ifdef FMD_ONENAND  // Configure CS0 for OneNAND,  Base Address 0x0C000000  OUTREG32(&pGpmc->GPMC_CONFIG1_0, BSP_GPMC_ONENAND_CONFIG1);  OUTREG32(&pGpmc->GPMC_CONFIG2_0, BSP_GPMC_ONENAND_CONFIG2);  OUTREG32(&pGpmc->GPMC_CONFIG3_0, BSP_GPMC_ONENAND_CONFIG3);  OUTREG32(&pGpmc->GPMC_CONFIG4_0, BSP_GPMC_ONENAND_CONFIG4);  OUTREG32(&pGpmc->GPMC_CONFIG5_0, BSP_GPMC_ONENAND_CONFIG5);  OUTREG32(&pGpmc->GPMC_CONFIG6_0, BSP_GPMC_ONENAND_CONFIG6);  OUTREG32(&pGpmc->GPMC_CONFIG7_0, BSP_GPMC_ONENAND_CONFIG7); #endif #ifdef FMD_NAND  // Configure CS0 for NAND,  Base Address 0x08000000  OUTREG32(&pGpmc->GPMC_CONFIG1_0, BSP_GPMC_NAND_CONFIG1);  OUTREG32(&pGpmc->GPMC_CONFIG2_0, BSP_GPMC_NAND_CONFIG2);  OUTREG32(&pGpmc->GPMC_CONFIG3_0, BSP_GPMC_NAND_CONFIG3);  OUTREG32(&pGpmc->GPMC_CONFIG4_0, BSP_GPMC_NAND_CONFIG4);  OUTREG32(&pGpmc->GPMC_CONFIG5_0, BSP_GPMC_NAND_CONFIG5);  OUTREG32(&pGpmc->GPMC_CONFIG6_0, BSP_GPMC_NAND_CONFIG6);  OUTREG32(&pGpmc->GPMC_CONFIG7_0, BSP_GPMC_NAND_CONFIG7); #endif

 // Configure CS6 for LAN,  Base Address 0x15000000  OUTREG32(&pGpmc->GPMC_CONFIG1_6, BSP_GPMC_LAN_CONFIG1);  OUTREG32(&pGpmc->GPMC_CONFIG2_6, BSP_GPMC_LAN_CONFIG2);  OUTREG32(&pGpmc->GPMC_CONFIG3_6, BSP_GPMC_LAN_CONFIG3);  OUTREG32(&pGpmc->GPMC_CONFIG4_6, BSP_GPMC_LAN_CONFIG4);  OUTREG32(&pGpmc->GPMC_CONFIG5_6, BSP_GPMC_LAN_CONFIG5);  OUTREG32(&pGpmc->GPMC_CONFIG6_6, BSP_GPMC_LAN_CONFIG6);  OUTREG32(&pGpmc->GPMC_CONFIG7_6, BSP_GPMC_LAN_CONFIG7);

 // check global reset status  val = INREG32(&pPrmGlobal->PRM_RSTST);

 if (val & (GLOBAL_SW_RST | EXTERNAL_WARM_RST))   bColdBoot = FALSE;  else   bColdBoot = TRUE;

 // read config register  INREG32(&pSdrc->SDRC_SYSCONFIG);

 // Disable SDRC power saving mode  CLRREG32(&pSdrc->SDRC_POWER, SDRC_POWER_PWDENA);

 // update memory cofiguration  OUTREG32(&pSdrc->SDRC_MCFG_0, BSP_SDRC_MCFG_0);  OUTREG32(&pSdrc->SDRC_MCFG_1, BSP_SDRC_MCFG_1);  OUTREG32(&pSdrc->SDRC_SHARING, BSP_SDRC_SHARING);

 // wait for at least 200us  OALStall(2000);

 // set autorefresh  OUTREG32(&pSdrc->SDRC_RFR_CTRL_0, BSP_SDRC_RFR_CTRL_0);  OUTREG32(&pSdrc->SDRC_RFR_CTRL_1, BSP_SDRC_RFR_CTRL_1);

 // setup ac timings  OUTREG32(&pSdrc->SDRC_ACTIM_CTRLA_0, BSP_SDRC_ACTIM_CTRLA_0);  OUTREG32(&pSdrc->SDRC_ACTIM_CTRLA_1, BSP_SDRC_ACTIM_CTRLA_1);  OUTREG32(&pSdrc->SDRC_ACTIM_CTRLB_0, BSP_SDRC_ACTIM_CTRLB_0);  OUTREG32(&pSdrc->SDRC_ACTIM_CTRLB_1, BSP_SDRC_ACTIM_CTRLB_1);   

 // manual command sequence to start bank 0  OUTREG32(&pSdrc->SDRC_MANUAL_0, 0);  // wait for at least 200us  OALStall(2000);  OUTREG32(&pSdrc->SDRC_MANUAL_0, 1);  OUTREG32(&pSdrc->SDRC_MANUAL_0, 2);  OUTREG32(&pSdrc->SDRC_MANUAL_0, 2);  OUTREG32(&pSdrc->SDRC_MR_0, BSP_SDRC_MR_0);

#if BSP_RAMSIZE_1  // manual command sequence to start bank 1  OUTREG32(&pSdrc->SDRC_MANUAL_1, 0);  // wait for at least 200us  OALStall(2000);  OUTREG32(&pSdrc->SDRC_MANUAL_1, 1);  OUTREG32(&pSdrc->SDRC_MANUAL_1, 2);  OUTREG32(&pSdrc->SDRC_MANUAL_1, 2);  OUTREG32(&pSdrc->SDRC_MR_1, BSP_SDRC_MR_1); #endif

 OUTREG32(&pSdrc ->SDRC_CS_CFG, 2);  // re-enable power saving mode  SETREG32(&pSdrc->SDRC_POWER, SDRC_POWER_PWDENA | SDRC_POWER_SRFRONIDLEREQ);

 // update sdrc dll timings  OUTREG32(&pSdrc->SDRC_DLLA_CTRL, BSP_SDRC_DLLA_CTRL);  OUTREG32(&pSdrc->SDRC_DLLB_CTRL, BSP_SDRC_DLLB_CTRL);

 // update sdram characteristics  OUTREG32(&pSdrc->SDRC_EMR2_0, BSP_SDRC_EMR2_0);  OUTREG32(&pSdrc->SDRC_EMR2_1, BSP_SDRC_EMR2_1);      SETREG32(&pSdrc->SDRC_POWER, SDRC_POWER_SRFRONRESET);

 // allow SDRC to settle  OALStall(100);

 // release the force on the clke signals  OUTREG16(&pConfig->CONTROL_PADCONF_SDRC_CKE0, (INPUT_DISABLE | PULL_INACTIVE | MUX_MODE_0));  OUTREG16(&pConfig->CONTROL_PADCONF_SDRC_CKE1, (INPUT_DISABLE | PULL_INACTIVE | MUX_MODE_0));

I copied this straight from the XLDR bootloader :

static VOID MemorySetup()

to DM9000DBG_Init method, with no success as we discussed ...

Hope this helps

I mis-typed my mail id with an extra dot. Correct one: renjith.thomas@pathpartnertech.com. 

Franck Agogue said:

Is there a double map, with 0x1500000 to write to registers, and 0x15000400 to read the content back ?

This depends on the interface. If the address bit A10 is connected to the R/W selection pin of DM9000, then having different address will automatically differentiate read/write. You don't to a strobe for read in particular. Can you verify the interface by checking the schematics? If its not connected properly, then read will not work. If you can share the schematics, I can verify the same. 

Since the value of dwIndexPortAddress is having 0x1500_0000, which is a physical address, can you explicitly do a dwIndexPortAddress = OALPAtoUA(dwIndexPortAddress); and see the updated value of dwIndexPortAddress? If it is a virtual address above 0x8000_0000, the do the same for dwDataPortAddress.

Also what are the values defined for BSP_GPMC_LAN_CONFIG1-7?

Franck,

If you can share one board I could have fixed it for you in just one day. 

Renjith,

Thanks a lot for your suggestion. However, I lear a lot in the debug process...

Also Ido not have a spare card, and it wuld take awhile to reach yu (where are you b the way ? )

The LAN settings are the following:

//  LAN9115 settings

//  165ns minimum cycle time for back to back accesses

//      32ns min CS, OE, WE assertion

//      13ns min deassertion

//  supports paged bursts, disabled for now

#define BSP_GPMC_LAN_CONFIG1       0x00001000       // no wait, 16 bit, non multiplexed

#define BSP_GPMC_LAN_CONFIG2       0x00080800       // CS OffTime 48ns

#define BSP_GPMC_LAN_CONFIG3       0x00020201       // we don't use ADV

#define BSP_GPMC_LAN_CONFIG4       0x08000800       // Deassert #WE, #OE at 48ns

#define BSP_GPMC_LAN_CONFIG5       0x01060D0D       // Cycle time 78ns, access time 36ns

#define BSP_GPMC_LAN_CONFIG6       0x00000F80       // Delay 90ns between successive accesses to meet minimum cycle time

#define BSP_GPMC_LAN_CONFIG7       0x00000F55       // Base address 0x15000000, 16MB window

I wll try to foce the inex in virtual meory space with OALPAtoUA

talk to you soon...

Franck

Franck,

I'm based out of Bangalore, India. Details are there in my e2e profile.

...

also regading schematics,

the bootloader can read the DM9000 registers, so I really beliee the problem is in the virtual meory mapping...

Renjith,

This is very muc the problem:

with physical address 0x15000000,

OALPAtoUA return 0x00fe00fe

according to the addrtab_cfg.inc file, I guess it should return a virtual address @ 0x8D00 0000

IF BSP_SDRAM_BANK1_ENABLE <> 1

am I right ?

I wll hard code index = 0x8D00 0000 to see what happens...

Franck,

0x8D00_0000 is a cached address. I think you should 0xAD00_0000 for uncached access or 0xCD00_0000. I'm not able to recollect the logic followed in setting up page table. Long time, not seeing wince code.