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DM81xx/AM389x - interface Marvell 88E6182 via GMII and boot?

AnBer
Mastermind 30120 points
Other Parts Discussed in Thread: AM3894

Team,

Could you please have a look at the below question:

Question regarding the Ethernet GMII interface:

Trying to connect GMII to the Marvell 88E6182 Ethernet switch via its Reverse GMII port. This interface will only be run in gigabit full-duplex mode. From errata  DM8168/AM3894 must have a clock present at TX_CLK for the device to boot from LAN in gigabit mode.

 

1)Can async  EMAC[0]_GMCLK be used output to clock the Switch RX_CLK (egress path) then loop back to the TX_CLK ARM pin? What are the timing relations if any to the TXD[0..7] bus

 

2)As the switch sources the ingress data bus RXD[0..7] with a GTX_CLK which I connect to RX_CLK, can this clock signal be used to go to the TXCLK pin then be tracked (and length matched) with the TXD[7..0] back to the switch?

 

Will either of these proposals work for errata issue and will it be bootable from Gigabit LAN with these methods?

Thanks and best regards,

Anthony

  • 0
    TI__Mastermind 30120 points

    From what I understood trying to answer my previous post:

    1) The bottom line is that the ROM bootloader code expects the TXCLK to be driven by the PHY and it configures the EMAC controller for that mode (it means it will operate in MII mode). This mean that TXCLK need to comply to the IEEE 802.3 standard in term of timings.
    If the 88E6182 switch is able to come up in 10/100Mbit mode (meaning that it will generate TXCLK) then it should be ok.

    The GTX_CLK and RX_CLK (terminology used in the standard) seem to be asynchronous and there is no mention at all of TX_CLK in the GMII standard. I don't think it is realistic to re-use RX_CLK to generate TX_CLK because of timings. Anyway the ROM bootlader expects to be connected to the PHY via an MII interface.

    More information in the below E2E post:
    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/128095.aspx

    2)The same issue as described in 1) meaning that GEMAC need to operate in MII mode during the bootload. Then at run time (after boot) GMII can be used.

    Note: it is not only about ROM bootload. At run time if EMAC is disabled/enabled again then it assumes MII to start with. Then you can use auto-negotiation to go into GMII mode to support 1Gbit operation.