C672x EMIF Asynchronous Space Question

Julxhino Gocllari

Hi,

I'm experimenting with the C6720 on a custom built board and I'm booting in parallel flash mode via an 8-bit parallel flash(SST39LF040). It boots up fine and some sample programs have worked ok, but when I try to read a word from the flash by saying something like this(not actual code, just an example):

#define TOP_OF_ASYNCHRONOUS 0x90000000

#define TOP_OF_INTERNAL_RAM 0x10000000

LDW .D1 A0, 0x90000004 //Load the contents of memory location 0x90000004 into A0

//4 junk instructions in between to satisfy functional unit latency for the load instruction

LDW .D1 A1, 0x10000004 //Load Contents of memory location 0x10000004 into A1

Since I'm booting in parallel flash mode, shouldn't the contents of 0x90000004 and 0x100000004 be the same right after boot up? I have verified that they are not and I'm not really sure why, I've programmed A1CR with its proper values, I've also programmed all of the SDRAM registers accordingly. I can read and write from SDRAM fine, but I can't seem to be able to read from my flash. I also viewed the EM_CS[2] pin on the oscilloscope, while running an infinite loop which tried reading from flash, and the EM_CS[2] pin NEVER went low, while the EM_CS[0] pin was low all the time. I never touch the cache registers, I also never touch the CSR(control register) which has the settings for the cache. Could that have something to do with my problem?

Any comments/tips/answers would be greatly appreciated

over 12 years ago

0 Jakez over 12 years ago

Expert 1950 points

Hello,

Some advice:

At boot time, the first KB of flash EPROM is copied at start of internal RAM: without writing at 0x10000004, the RAM&flash values must be the same.

As the C6720 has only a program cache, data reads are unaffected by cache status (CSR,...).

From the above information, CS2 should toggle. If not, some assumption is false; a bad code in the loop test seems the most probable to me (since you seem having no access to an emulator), leading to a read from a wrong address.

Let the community help you, please give full brute information, especially the A1CR value and the real instructions sequence used for the endless test loop (not a pseudo-code), for example:

MVKL 0x0004,A2 ; (0x0004 -> A2)

MVKLH 0x9000,A2 ; (0x9000 -> 16 MSB of A2)

loop: B loop

LDW *A2,A0

NOP 4

; A0 loaded and effective branch here

By the way, there is no functional unit latency on single-word reads, only a 4-cycle delay; you can write:

LDW *A2,A0

LDW *A3,A1

NOP 3

; A0 loaded here

NOP

; A1 loaded here

Jakez

0 Julxhino Gocllari over 12 years ago in reply to Jakez

Prodigy 105 points

Jakez,

Thank you so much for your advice and help. I have found the problem and it had nothing to do with the hardware, as it usually is, the issue was on custom assembler! =(. The funny thing is that I had to communicate with a PIC18F4550 via I2C to read some of the internal registers, to make sure that everything was ok internally and guess what it wasn't, It turns out that when I was using the MVKL and MVKH instructions, my MVKH instruction was translating 0x9000XXXX into 0x8000XXXX, which explains why I was reading SDRAM all the time. Nonetheless I'd like to thank you for your input once again

Julxhino

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C672x EMIF Asynchronous Space Question