EMAC1 LINK interrupt

/*
*/

#include <emac.h>
#include <mdio.h>
#include <lan8710a.h>
#include "types.h"
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>

#include "fns_driver.h"

#include "errcodes.h"
#include "sock\sock_utils.h"
#include "lan_interface.h"


#include "BBeth1.h"

#define CONFIG_NET_POLL_CONTROLLER
#define virtual(val) (val - 0x80000000)
#define physical(val) (val + 0x80000000)
//#define	DEBUG_DUMP_PACKETS
/*
 *  NAPI poll function
 */

#ifdef DEBUG_DUMP_PACKETS
static void emac_dump_packets(U8 *ptr, U16 len)
{
	int i = 0;

	for (i=0;i<len;i++)
		com_printf(" %X",ptr[i]);
	com_printf("\n");
}
#endif

static int emac_poll(struct net_device *dev)
{
	EMAC_DATA *pdata;
	RXCH *rxch;
	volatile EMAC_RX_BD *curr_bd,*last_bd,*processed_bd;
	U32 ex_len = 0, len_to_alloc = 0;
	U16 tot_len = 0,len = 0;
	U8  *ptr, *buf_ptr;
	int err;

	pdata = netdev_priv(dev);
	rxch = &(pdata->rxch);

	curr_bd = rxch->active_head;
	// Get the bd which contains the earliest filled data

	// Process the descriptors as long as data is available
	// when the DMA is receiving data, SOP flag will be set
	while(curr_bd->flags_pktlen & EMAC_BUF_DESC_SOP)
	{
		ex_len = 0;
	    len_to_alloc = 0;

	    // Start processing once the packet is loaded
	    if(EMAC_BUF_DESC_OWNER != (curr_bd->flags_pktlen & EMAC_BUF_DESC_OWNER))
	    {
	    	// Get the total length of the packet. curr_bd points to the start
	    	// of the packet.
	    	tot_len = (curr_bd->flags_pktlen) & 0xFFFF;
	    	do
	    	{
	    		last_bd = rxch->active_tail;

	    		ptr = (U8*)virtual(curr_bd->bufptr);
	    		len = (curr_bd->bufoff_len) & 0xFFFF;
#ifdef DEBUG_DUMP_PACKETS
	    		com_printf("RECV: ");
	    		emac_dump_packets(ptr, len);
#endif //DEBUG_DUMP_PACKETS
#ifdef OS_TARGET
	    		if( dev->i_devID == 0 )
	    		{
	    			communication_interrupt_bb_other_counter ++;
	    			total_not_bb1_pkts ++;
	    		}
	    		if( 1 == dev->i_devID && is_packet_backbone(ptr, len) )
	    		{
	    			Eth_Backbone_operation(dev, (char *)ptr, len);
	    		}
	    		else
#endif
	    			if( FNS_ENOERR != fnsNetDevUpcall(dev->ndp, (char *)ptr, len) )
	    			{
	    				EMAC_WARNING("ERROR fnsNetDevUpcall\n");
	    			}
	    			else
	    			{
	    				buf_ptr = (U8*)fnsNetDevAllocBuffer( dev->ndp, MAX_TRANSFER_UNIT, &err );
	    				if( FNS_ENOERR == err)
	    				{
	    					// Replace the message we up-called with the new one
	    					curr_bd->bufptr = (u32)physical(buf_ptr);
	    				}
	    				else
	    				{
	    					EMAC_WARNING("ERROR fnsNetDevAllocBuffer %d\n",err);
	    				}
	    			}

	    		// clear flags and values
	    		last_bd->flags_pktlen = EMAC_BUF_DESC_OWNER;
	    		last_bd->bufoff_len = MAX_TRANSFER_UNIT;
	    		// set next bd
	    		processed_bd = curr_bd;
	    		curr_bd = curr_bd->next;

	    		// As processed_bd was just processed now it became last bd in circle list.
	    		// previous last bd next flag now points to processed bd.
	    		last_bd->next = processed_bd;
	    		// move active head pointer to next value
	    		rxch->active_head = processed_bd->next;
	    		// set tail to processed bd
	    		rxch->active_tail = processed_bd;
	    		// set next pointer of last bd to NULL
	    		processed_bd->next = NU_NULL;
	    	} while((processed_bd->flags_pktlen & EMAC_BUF_DESC_EOP)
	                != EMAC_BUF_DESC_EOP);

	    	// Acknowledge that this packet is processed
	    	EMACRxCPWrite(pdata->emac_base, 0, (unsigned int)processed_bd);

	        // Check if the reception has ended. If the EOQ flag is set, the NULL
	    	// Pointer is taken by the DMA engine. So we need to write the RX HDP
	    	// with the next descriptor.
	    	if(processed_bd->flags_pktlen & EMAC_BUF_DESC_EOQ)
	    	{
	    		EMACRxHdrDescPtrWrite(pdata->emac_base, (U32)(rxch->active_head), 0);
	    	}
		}
	    curr_bd = rxch->active_head;
	}
	return tot_len;
}

static void _emac_inst_config(EMAC_DATA *pdata)
{
	if(pdata->inst_num == 0)
	{
		pdata->emac_base = EMAC_0_BASE;
		pdata->emac_ctrl_base = EMAC_CTRL_0_BASE;
		pdata->emac_ctrl_ram = EMAC_CTRL_RAM_0_BASE;
		pdata->mdio_base = MDIO_0_BASE;
#warning "pdata->phy_addr = 1 for ev.board and pdata->phy_addr = 6 for prot.board"
#warning "pdata->phy_addr = 4 with FPGA and pdata->phy_addr = 6 for withot FPGA"

		pdata->phy_addr = 4;//1;
		pdata->phy_autoneg = Lan8710aAutoNegotiate;
		pdata->phy_partnerability = Lan8710aPartnerAbilityGet;
	}
	else if (pdata->inst_num == 1)
	{
		pdata->emac_base = EMAC_1_BASE;
		pdata->emac_ctrl_base = EMAC_CTRL_1_BASE;
		pdata->emac_ctrl_ram = EMAC_CTRL_RAM_1_BASE;
		pdata->mdio_base = MDIO_0_BASE;
		pdata->phy_addr = 1;
		#warning "pdata->phy_addr = 1 with FPGA and pdata->phy_addr = 3 for withot FPGA"
		pdata->phy_autoneg = Lan8710aAutoNegotiate;
		pdata->phy_partnerability = Lan8710aPartnerAbilityGet;
	}
	else
	{
		EMAC_WARNING("pdata->inst_num invalid - %d",pdata->inst_num);
	}
	pdata->broadcast_on = 0;
	pdata->storm_control_counter = 0;
	pdata->link_is_up = 0;
}

static int _emac_link_setup(EMAC_DATA *pdata)
{
	STATUS linkstat = -1;
	U16 partnr_ablty;
	U32 phyduplex;

	phyduplex = EMAC_DUPLEX_HALF;
	// Start link setup
	if(Lan8710aAutoNegotiate(pdata->mdio_base, pdata->phy_addr,
			(LAN8710A_100BTX | LAN8710A_100BTX_FD | LAN8710A_10BT | LAN8710A_10BT_FD)) == TRUE)
	{
		U32 speed = 0;

		linkstat = NU_SUCCESS;
		// Check speed value after autonegotiation finished
		speed = Lan8710aSpeedAbilityGet(pdata->mdio_base, pdata->phy_addr);

		if ( 0 != speed )
		{
			EMAC_TRACE( "Connection speed %d mbps\n",speed);
			// Turn on/off gig mode.
			if (1000 == speed)
			{
				EMACGIGEnable(pdata->emac_base);
			}
			else
			{
				EMACGIGDisable(pdata->emac_base);
			}

			Lan8710aPartnerAbilityGet(pdata->mdio_base, pdata->phy_addr,
						&partnr_ablty);

			// Check for 100 Mbps and duplex capability
			// In 1000 Mbps full duplex mode supported only
			if((1000 == speed) || (partnr_ablty & LAN8710A_100BTX_FD))
			{
				phyduplex = EMAC_DUPLEX_FULL;
			}
		}
		else
		{
			EMAC_WARNING( "Connection speed illegal\n");
			linkstat = -1;
		}
	}
	else
	{
		EMAC_WARNING( "autonegotiate error\n");
		linkstat = -1;
	}

	/* Set the EMAC with the negotiation results if it is successful */
	if(linkstat == NU_SUCCESS)
	{
		EMACDuplexSet(pdata->emac_base, phyduplex);
	}

	/* Wait for the MII to settle down */
	NU_Sleep(10);

	return linkstat;
}

/* Update link mode if any thing has changed */
static void emac_misc(struct net_device *dev)
{
	EMAC_DATA *pdata;
	pdata = netdev_priv(dev);
	int irq = 0;

	irq = EMACIntVectorGet(pdata->emac_base);
////////////////////////////////////////////////
#warning "Temporary fix, while EMAC1_MISC interrupt not working. Comment this for ev.board"
	if (1 == dev->i_devID)
		irq = EMAC_MACINVECTOR_LINKINT0;
////////////////////////////////////////////////
	switch(irq)
	{
		case EMAC_MACINVECTOR_LINKINT0:
		{
			// Check link status in EMAC level
			int index = MDIOAckLinkInt(pdata->mdio_base);
			int link_is_up = 0;

			//if (index != pdata->phy_addr)
				//break;
			// Check if emac still alive
			if(!((MDIOPhyAliveStatusGet(pdata->mdio_base) >> pdata->phy_addr) & 0x01 ))
			{
				EMAC_WARNING( "MDIOPhyAliveStatusGet error\n");
				pdata->link_is_up = 0;
				break;
			}
			// Second link check - in PHY level
			link_is_up = Lan8710aLinkStatusGet(pdata->mdio_base, pdata->phy_addr, 10000);

			if (pdata->link_is_up != link_is_up)
			{
				pdata->link_is_up = link_is_up;
				if(pdata->link_is_up)
				{
					// Start link setup (autonegotiation)
					if(NU_SUCCESS != _emac_link_setup(pdata))
					{
						EMAC_WARNING( "_emac_link_setup error\n");
						pdata->link_is_up = 0;
						break;
					}
					EMAC_TRACE( "link is up! \n");
					fnsNetDevIsUp( dev->ndp );
				}
				else
				{
					EMAC_TRACE( "link is down!\n");
					fnsNetDevIsDown( dev->ndp );
				}
			}
			break;
		}
		case EMAC_MACINVECTOR_STATPEND:
		{
			// for future use
			break;
		}
		case EMAC_MACINVECTOR_USERINT0:
		{
			// for future use
			break;
		}
		case EMAC_MACINVECTOR_HOSTPEND:
		{
			// for future use
			break;
		}
		default:
			break;
	}
}

static int emac_open(struct net_device *dev)
{
	U32 channel;
	U32 num_bd;
	volatile EMAC_TX_BD *curr_txbd, *last_txbd;
	volatile EMAC_RX_BD *curr_bd, *last_bd;
	EMAC_DATA *pdata;
	TXCH *txch;
	RXCH *rxch;
	char *p;
	int err;
	U8 hw_addr[6];

	pdata = netdev_priv(dev);

	// device capabilities
	EMACInit(pdata->emac_ctrl_base, pdata->emac_base);

	MDIOInit(pdata->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT);
	NU_Sleep(1);

	EMACRxBroadCastEnable(pdata->emac_base, 0);

	// Set the MAC Addresses in EMAC hardware
	hw_addr[0] = dev->dev_mac_addr[5];
	hw_addr[1] = dev->dev_mac_addr[4];
	hw_addr[2] = dev->dev_mac_addr[3];
	hw_addr[3] = dev->dev_mac_addr[2];
	hw_addr[4] = dev->dev_mac_addr[1];
	hw_addr[5] = dev->dev_mac_addr[0];

	EMACMACSrcAddrSet(pdata->emac_base, hw_addr);

	for(channel = 0; channel < 8; channel++)
	{
		EMACMACAddrSet(pdata->emac_base, channel, hw_addr, EMAC_MACADDR_MATCH);
	}

	// Initialize the Descriptor Memory For TX and RX
	// Only Channel 0 is supported for both TX and RX

	txch = &(pdata->txch);

	txch->free_head = (volatile EMAC_TX_BD*)(pdata->emac_ctrl_ram);
	txch->next_bd_to_process = txch->free_head;
	txch->active_tail = NULL;

	// Set the number of descriptors for the channel
	num_bd = (SIZE_EMAC_CTRL_RAM >> 1) / sizeof(EMAC_TX_BD);

	curr_txbd = txch->free_head;

	// Initialize all the TX buffer Descriptors
	while(num_bd--)
	{
		curr_txbd->next = curr_txbd + 1;
		curr_txbd->flags_pktlen = 0;
		last_txbd = curr_txbd;
		curr_txbd = curr_txbd->next;
	}
	last_txbd->next = txch->free_head;

	// Initialize the descriptors for the RX channel
	rxch = &(pdata->rxch);
	rxch->active_head = (volatile struct EMAC_RX_BD*)(curr_txbd + 1);

	// Set the number of descriptors for the channel
	num_bd = ((SIZE_EMAC_CTRL_RAM >> 1) / sizeof(EMAC_RX_BD) - 1);
	curr_bd = rxch->active_head;
	last_bd = curr_bd;

	// Allocate the pbufs for the maximum count permitted or till the
	// number of buffer desceriptors expire, which ever is earlier.
	while(num_bd--)
	{
		p = fnsNetDevAllocBuffer( dev->ndp, MAX_TRANSFER_UNIT, &err );
		if( FNS_ENOERR == err )
		{
			curr_bd->bufptr = (U32)physical(p);
			curr_bd->bufoff_len = MAX_TRANSFER_UNIT;
			curr_bd->next = curr_bd + 1;
			curr_bd->flags_pktlen = EMAC_BUF_DESC_OWNER;

			/* Save the pbuf */
			last_bd = curr_bd;
			curr_bd = curr_bd->next;
		}
     }

	last_bd->next = NULL;
	rxch->active_tail = last_bd;

	/* Enable PHY to clock out TX_CLK for gigabit transmit*/

	short unsigned int tmp = 0;

	Lan8710aRegRead(pdata->mdio_base, pdata->phy_addr, PHY_CONF_REG, &tmp);
	tmp |= PHY_CONF_TXCLKEN;
	Lan8710aRegWrite(pdata->mdio_base, pdata->phy_addr, PHY_CONF_REG, tmp);
	Lan8710aRegRead(pdata->mdio_base, pdata->phy_addr, PHY_CONF_REG, &tmp);

	// Acknowledge receive and transmit interrupts for proper interrupt pulsing
	EMACCoreIntAck(pdata->emac_base, EMAC_INT_CORE0_RX);
	EMACCoreIntAck(pdata->emac_base, EMAC_INT_CORE0_TX);
	EMACCoreIntAck(pdata->emac_base, EMAC_INT_CORE0_MISC);

	EMACRxUnicastSet(pdata->emac_base, 0);
	EMACNumFreeBufSet(pdata->emac_base, 0, 10);

	EMACTxEnable(pdata->emac_base);
	EMACRxEnable(pdata->emac_base);
#warning "For correct WP_Line working on ev.board use MISC int. for Park only.Just uncomment two lines"
	//if (0 == pdata->inst_num)
	//	MDIOSetLinkInt(pdata->mdio_base, 0, pdata->phy_addr);
	MDIOSetLinkInt(pdata->mdio_base, pdata->inst_num, pdata->phy_addr);
	// Write the RX HDP for channel 0
	EMACRxHdrDescPtrWrite(pdata->emac_base, (U32)rxch->active_head, 0);

	EMACMIIEnable(pdata->emac_base);
/////////////////
#warning "Temporary fix, while EMAC1_MISC interrupt not working. Comment this for ev.board"
	if (1 == pdata->inst_num)
		emac_misc(dev);
/////////////////
	// Enable the Transmission and reception, enable the interrupts for
	// channel 0 and for control core 0
	EMACTxIntPulseEnable(pdata->emac_base, pdata->emac_ctrl_base, 0, 0);
	EMACRxIntPulseEnable(pdata->emac_base, pdata->emac_ctrl_base, 0, 0);
	// Turn on misc interrupts: STAT = 0x8, HOST = 0x4, LINK = 0x2, USER = 0x1
#warning "For correct WP_Line working on ev.board use MISC int. for Park only. Just uncomment \"if\" line"
  //if (0 == pdata->inst_num)
		EMACMiscIntPulseEnable(pdata->emac_ctrl_base, 0, 0x2);

	return NU_SUCCESS;
}

int emac_stop(struct net_device *dev)
{
	EMAC_DATA *pdata = netdev_priv(dev);

	EMACTxTearDown(pdata->emac_base);
	EMACRxTearDown(pdata->emac_base);

	EMACInit(pdata->emac_ctrl_base, pdata->emac_base);
    return 0;
}

static int emac_no_buf_hard_start_xmit( struct m *buf_ptr )
{
	TXCH *txch;
    net_device *dev  = GetLanDevInfo(buf_ptr->m_ndp);
    EMAC_DATA *pdata = netdev_priv(dev);
	volatile EMAC_TX_BD *curr_bd, *active_head, *bd_end;
	int len_tot = 0, len = 0, i = 0;
	U32 position = -1;
	U8  *ptr;

	dev->LockSemaphore(dev);
    // Total message length count
    if( buf_ptr->m_cell_count > 0 )
       	len_tot = buf_ptr->m_total_dlen + buf_ptr->m_ptail - buf_ptr->m_hp;
    else
    	len_tot = (m_dsize(buf_ptr));

	if( len_tot > 1514 || len_tot == 0 )
	{
		EMAC_WARNING( "Error total packet length=%d", len_tot );
		dev->UnockSemaphore(dev);
		return -1;
	}

    if( len_tot < MIN_PACKET_LENGTH )
           len_tot = MIN_PACKET_LENGTH;

	txch = &(pdata->txch);

	// Get the buffer descriptor which is free to transmit
	curr_bd = txch->free_head;
	// Save start address of transmit list
	active_head = curr_bd;
    // Get header address
    ptr = (U8*)buf_ptr->m_hp;
    // Header length count
    if( buf_ptr->m_cell_count > 0 )
    	len = m_hsize(buf_ptr);
    else
    	len = len_tot;

    position = len;
#ifdef DEBUG_DUMP_PACKETS
	    		com_printf("SEND 0: ");
	    		emac_dump_packets(ptr, len);
#endif //DEBUG_DUMP_PACKETS
	// Update the total packet length
	curr_bd->flags_pktlen &= ~0xFFFF;
	curr_bd->flags_pktlen |= len_tot;
	// Indicate the start of the packet
	curr_bd->flags_pktlen |= (EMAC_BUF_DESC_SOP | EMAC_BUF_DESC_OWNER);

	// Copy pbuf information into TX buffer descriptors
	curr_bd->bufptr = (U32)physical(ptr);
	curr_bd->bufoff_len = len & 0xFFFF;
    bd_end = curr_bd;
    curr_bd = curr_bd->next;

	// Copy pbuf information into TX buffer descriptors
	// Send user data
    if( buf_ptr->m_cell_count > 0 )
    {
    	for( i = 0; i < buf_ptr->m_cell_count; i++ )
    	{
    		ptr = (U8*)buf_ptr->m_datacells[i].celldata;
    		len = (U32)buf_ptr->m_datacells[i].cellsize;
#ifdef DEBUG_DUMP_PACKETS
	    		com_printf("SEND %d: ",i+1);
	    		emac_dump_packets(ptr, len);
#endif //DEBUG_DUMP_PACKETS
	    	curr_bd->bufptr = (U32)physical(ptr);
    	    curr_bd->bufoff_len = len & 0xFFFF;
    	    bd_end = curr_bd;
    	    curr_bd = curr_bd->next;
    	    position += len;
    	}
    }

	// Indicate the end of the packet
	bd_end->next = NULL;
	bd_end->flags_pktlen |= EMAC_BUF_DESC_EOP;

	// check if sum of all length not less then 60
	if (position < MIN_PACKET_LENGTH)
		bd_end->bufoff_len += (MIN_PACKET_LENGTH-position);

	txch->free_head = curr_bd;

	// For the first time, write the HDP with the filled bd
	if(txch->active_tail == NULL)
	{
	    EMACTxHdrDescPtrWrite(pdata->emac_base, (unsigned int)(active_head), 0);
	}

	// Chain the bd's. If the DMA engine, already reached the end of the chain,
	// the EOQ will be set. In that case, the HDP shall be written again.

	else
	{
		curr_bd = txch->active_tail;
	    curr_bd->next = active_head;
	    if(curr_bd->flags_pktlen & EMAC_BUF_DESC_EOQ)
	    {
	      // Write the Header Descriptor Pointer and start DMA
	      EMACTxHdrDescPtrWrite(pdata->emac_base, (unsigned int)(active_head), 0);
	    }
	}
	txch->active_tail = bd_end;

	dev->UnockSemaphore(dev);
    return position;
}

/* Entry point for transmitting a packet */
static int emac_hard_start_xmit( void *ptr__t, int len__t, struct net_device *dev)
{
	TXCH *txch;
    EMAC_DATA *pdata = netdev_priv(dev);
	volatile EMAC_TX_BD *curr_bd, *active_head, *bd_end;
	U8  *ptr;
	int len = 0;
	int err;
	dev->LockSemaphore(dev);

	if( len__t > 1514 || len__t == 0 )
	{
		EMAC_WARNING( "Error total packet length=%d", len__t );
		dev->UnockSemaphore(dev);
		return -1;
	}

    if( len < MIN_PACKET_LENGTH )
    	len = MIN_PACKET_LENGTH;
    else
    	len = len__t;

    // Allocate memory for packet
    ptr = (U8*)fnsNetDevAllocBuffer( dev->ndp, len, &err );
	if( FNS_ENOERR != err)
	{
		EMAC_WARNING("ERROR fnsNetDevAllocBuffer %d\n",err);
		dev->UnockSemaphore(dev);
		return -1;
	}
    memcpy(ptr,ptr__t,len);
	txch = &(pdata->txch);

	// Get the buffer descriptor which is free to transmit
	curr_bd = txch->free_head;
	// Save start address of transmit list
	active_head = curr_bd;

#ifdef DEBUG_DUMP_PACKETS
	    		com_printf("BBN SEND: ");
	    		emac_dump_packets(ptr, len);
#endif //DEBUG_DUMP_PACKETS
	/* Update the total packet length */
	curr_bd->flags_pktlen &= ~0xFFFF;
	curr_bd->flags_pktlen |= len;
	/* Indicate the start of the packet */
	curr_bd->flags_pktlen |= (EMAC_BUF_DESC_SOP | EMAC_BUF_DESC_OWNER | EMAC_BUF_DESC_EOP);

	/* Copy pbuf information into TX buffer descriptors */
    curr_bd->bufptr = (U32)physical(ptr);
    curr_bd->bufoff_len = len & 0xFFFF;
    bd_end = curr_bd;
    curr_bd = curr_bd->next;
    // Indicate the end of the packet
    bd_end->next = NULL;

	txch->free_head = curr_bd;

	/* For the first time, write the HDP with the filled bd */
	if(txch->active_tail == NULL)
	{
	    EMACTxHdrDescPtrWrite(pdata->emac_base, (unsigned int)(active_head), 0);
	}

	/*
	 * Chain the bd's. If the DMA engine, already reached the end of the chain,
	 * the EOQ will be set. In that case, the HDP shall be written again.
	 */
	else
	{
		curr_bd = txch->active_tail;
	    curr_bd->next = active_head;
	    if(curr_bd->flags_pktlen & EMAC_BUF_DESC_EOQ)
	    {
	      /* Write the Header Descriptor Pointer and start DMA */
	      EMACTxHdrDescPtrWrite(pdata->emac_base, (unsigned int)(active_head), 0);
	    }
	}
	txch->active_tail = bd_end;
	dev->UnockSemaphore(dev);

    return len__t;
}

static int emac_xmit_complete(struct net_device *dev)
{
	TXCH *txch;
	EMAC_DATA *pdata = netdev_priv(dev);
	volatile EMAC_TX_BD *curr_bd, *next_bd_to_process;

	txch = &(pdata->txch);
	next_bd_to_process = txch->next_bd_to_process;

	curr_bd = next_bd_to_process;

	// Check for correct start of packet
	while((curr_bd->flags_pktlen) & EMAC_BUF_DESC_SOP)
	{

		// Make sure that the transmission is over
		#warning "eternal cycle - need to break when packet wrong"
	    while((curr_bd->flags_pktlen & EMAC_BUF_DESC_OWNER) == EMAC_BUF_DESC_OWNER);

	    // Traverse till the end of packet is reached
	    while(((curr_bd->flags_pktlen) & EMAC_BUF_DESC_EOP) != EMAC_BUF_DESC_EOP)
	    {
	       curr_bd = curr_bd->next;
	    }

	    next_bd_to_process->flags_pktlen &= ~(EMAC_BUF_DESC_SOP);
	    curr_bd->flags_pktlen &= ~(EMAC_BUF_DESC_EOP);

	    // If there are no more data transmitted, the next interrupt
	    // shall happen with the pbuf associated with the free_head
	    if(curr_bd->next == NULL)
	    	txch->next_bd_to_process = txch->free_head;
	    else
	    	txch->next_bd_to_process = curr_bd->next;

	    // Acknowledge the EMAC
	    EMACTxCPWrite(pdata->emac_base, 0, (U32)curr_bd);
	    // Tell fusion that transmission is complete (not for bbn packets!)
#ifdef OS_TARGET
	    if( 1 == dev->i_devID && is_packet_backbone((U8*)virtual(curr_bd->bufptr),(curr_bd->bufoff_len)&0xFFFF) )
	    {
	    	fnsNetDevFreeBuffer( dev->ndp, (U8*)virtual(curr_bd->bufptr) );
	    }
	    else
#endif
	    {
	    	fnsNetDevTxComplete(dev->ndp);
	    }
	    next_bd_to_process = txch->next_bd_to_process;
	    curr_bd = next_bd_to_process;
	}
	return 0;
}

static ETH_DEVICE_STATS *emac_get_stats(struct net_device *dev)
{
	return &dev->stats;
}

static void emac_int_enable(struct net_device *p_dev)
{
	EMAC_DATA *pdata = NU_NULL;
	pdata = netdev_priv(p_dev);

	if (NU_NULL != pdata)
	{
		// Enable all active EMAC interrupts
		EMACTxIntPulseEnable(pdata->emac_base, pdata->emac_ctrl_base, 0, 0);
		EMACRxIntPulseEnable(pdata->emac_base, pdata->emac_ctrl_base, 0, 0);
		EMACMiscIntPulseEnable(pdata->emac_ctrl_base, 0, 0x2);
	}
}

static void emac_int_disable(struct net_device *p_dev)
{
	EMAC_DATA *pdata = NU_NULL;
	pdata = netdev_priv(p_dev);

	if (NU_NULL != pdata)
	{
		// Disable all active EMAC interrupts
		EMACTxIntPulseDisable(pdata->emac_base, pdata->emac_ctrl_base, 0, 0);
		EMACRxIntPulseDisable(pdata->emac_base, pdata->emac_ctrl_base, 0, 0);
		EMACMiscIntPulseDisable(pdata->emac_ctrl_base, 0, 0xF);
	}
}

static void emac_int_ack(struct net_device *p_dev, int vector)
{
	EMAC_DATA *pdata = NULL;
	if (NULL == p_dev)
	{
		return;
	}

	pdata = netdev_priv(p_dev);

	if ( ((0 == p_dev->i_devID) && (EMAC_RX_INT_0_VECTOR == vector)) ||
		 ((1 == p_dev->i_devID) && (EMAC_RX_INT_1_VECTOR == vector))  )
	{
		EMACCoreIntAck(pdata->emac_base, EMAC_INT_CORE0_RX);
	}
	if ( ((0 == p_dev->i_devID) && (EMAC_TX_INT_0_VECTOR == vector)) ||
	 	 ((1 == p_dev->i_devID) && (EMAC_TX_INT_1_VECTOR == vector))  )
	{
		EMACCoreIntAck(pdata->emac_base, EMAC_INT_CORE0_TX);
	}
	if ( ((0 == p_dev->i_devID) && (EMAC_RX_THR_0_VECTOR == vector)) ||
		 ((1 == p_dev->i_devID) && (EMAC_RX_THR_1_VECTOR == vector))  )
	{
		//for future use
	}
	if ( ((0 == p_dev->i_devID) && (EMAC_MISCEL_0_VECTOR == vector)) ||
		 ((1 == p_dev->i_devID) && (EMAC_MISCEL_1_VECTOR == vector))  )
	{
		EMACCoreIntAck(pdata->emac_base, EMAC_INT_CORE0_MISC);
	}
}

int emac_init(struct net_device *dev)
{
	/* Get the instance number first */
	EMAC_DATA *pdata;

	pdata = netdev_priv(dev);

	dev->LockSemaphore(dev);

	dev->open 					= emac_open;
	dev->stop 					= emac_stop;
	dev->hard_start_xmit 		= emac_hard_start_xmit;
	dev->no_buf_hard_start_xmit = emac_no_buf_hard_start_xmit;
	dev->get_stats 				= emac_get_stats;
	dev->misc 					= emac_misc;
	dev->poll 					= emac_poll;
	dev->xmit_complete 			= emac_xmit_complete;
	dev->int_enable				= emac_int_enable;
	dev->int_disable			= emac_int_disable;
	dev->int_ack				= emac_int_ack;

	pdata->inst_num = dev->i_devID;

	_emac_inst_config(pdata);
	dev->UnockSemaphore(dev);
	return 0;
}