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PCIe trouble to write/read ep bar0

serg05
Prodigy 200 points


Hi,

i have trouble to write in and read out the bar0 of my xilinx ep. The RC is c6678. To configure the RC I used the example program.

On the DSP side I have configured the Outbound address( PCIE_OB_LO_ADDR_M 0x70000000,PCIE_OB_HI_ADDR_M 0), Inbound address(PCIE_IB_LO_ADDR_M 0x90000000,PCIE_IB_HI_ADDR_M 0) and the EP FPGA

I disable the ACCR on the DSP side, because I am not sure if the xilinx ep handle it right.

To configure the ep I used the followed code in dsp.

/* Configure Address Translation */

barCfg.location = pcie_LOCATION_REMOTE;

barCfg.mode = pcie_EP_MODE;

barCfg.base = 0x70000000;

barCfg.prefetch = pcie_BAR_NON_PREF;

barCfg.type = pcie_BAR_TYPE32;

barCfg.memSpace = pcie_BAR_MEM_MEM;

barCfg.idx = 0;

if ((retVal = Pcie_cfgBar(handle, &barCfg)) != pcie_RET_OK)

{

System_printf ("Failed to configure BAR!\n");

exit(1);

}

memset (&PCIeCmdReg, 0, sizeof(PCIeCmdReg));

memset (&setRegs, 0, sizeof(setRegs));

PCIeCmdReg.memSp = 1;

PCIeCmdReg.busMs = 0;

PCIeCmdReg.serrEn = 1;

/* set everything to 1 */

PCIeCmdReg.parError = 0;

PCIeCmdReg.capList = 1;

PCIeCmdReg.resp = 1;

PCIeCmdReg.ioSp = 1;

setRegs.statusCmd= &PCIeCmdReg;

if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_REMOTE, &setRegs)) != pcie_RET_OK)

{

System_printf ("Read CMD STATUS register failed!\n");

}

To control the configuration I read at address (UInt32*)0x21802000 in C6678. The output is.

[C66xx_0] offset: 0x0 : 000710ee 00100143 05000000 00000000

[C66xx_0] offset: 0x10 : 70000000 00000000 00000000 00000000

[C66xx_0] offset: 0x20 : 00000000 00000000 00000000 000710ee

[C66xx_0] offset: 0x30 : 00000000 00000040 00000000 000001ff

[C66xx_0] offset: 0x40 : 00034801 00000000 00806005 00000000

[C66xx_0] offset: 0x50 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0x60 : 00010010 00008fea 00002810 0003f421

[C66xx_0] offset: 0x70 : 10210000 00000000 00000000 00000000

[C66xx_0] offset: 0x80 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0x90 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0xa0 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0xb0 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0xc0 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0xd0 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0xe0 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0xf0 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0x100 : 00010003 00000000 00000000 14410001

[C66xx_0] offset: 0x110 : 00000000 00000000 00062010 00000000

[C66xx_0] offset: 0x120 : 00002000 00000000 00000000 00000000

[C66xx_0] offset: 0x130 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0x140 : 00000000 10010004 00000000 00000000

[C66xx_0] offset: 0x150 : 00000000 00010002 00000000 00000000

[C66xx_0] offset: 0x160 : 00000000 00004000 800000ff 00000000

[C66xx_0] offset: 0x170 : 00004000 01000000 00020000 00000000

[C66xx_0] offset: 0x180 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0x190 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0x1a0 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0x1b0 : 00000000 00000000 00000000 00000000

[C66xx_0] offset: 0x1c0 : 00000000 00000000 00000000 00000000

If I write something on (Uint32*))0x7000xxxx and read afterward I get only zeros.

I have no further idea what could be wrong. It is possible that I mix up the addresses?

Regards serg05

  • 0
    TI__Genius 12065 points

    Serg,

    I think you posted something similar on the following thread as well.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/218446.aspx

    We could continue on either thread you prefer for this issue.

    My suggestion will be similar that you need to write data to the PCIe data space region (starting from 0x6000_0000 in C66x device) in order to send data out.

    For example, you write 0xFF to 0x6000_0000, it will translate to PCIe packet over the PCIe link with PCIe address 0x7000_0000 since you configure the OB address to be 0x7000_0000.

    When you read data from FPAG to DSP, you should read from 0x6000_0000 as well. Please make sure to use the 0x6000_0000~0x6FFF_FFFF as the PCIe data space in C66x for memory transactions. 

    The PCIe user guide and use case application note should have some examples on this. 

    Then the BAR0 in FPAG will accept this packet since you configure the BAR0 to be 0x7000_0000. And the data will arrive on the FPGA side and be routed to the memory region whatever BAR0 is pointed to (In C66x, it will be inbound translation. FPGA might use other mechanism).