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CSHOLD Problem using SPI with EDMA3

Patrick Ruf
Genius 4965 points
Other Parts Discussed in Thread: DAC8555

Hello

I use a C6748 Device and need to service a DAC8555 over SPI0 with the EDMA3. Because of the 24Bit Word of the DAC8555 I split the 24Bit into three 8 Bit transfers. For this to work one need to hold the CSn for the duration of all three transfers. Between the last transfer and the first transfer for the next channel (next 24Bits) the DAC8555 needs a delay. Therefore I have tried the following with the EDMA:

1. Write 0x10 to the highest byte in SPIDAT1
2. Write the first data byte to the lowest byte in SPIDAT1 (initiate the first transfer)
3. Write 0x10 to the highest byte in SPIDAT1
4. Write the second data byte to the lowest byte in SPIDAT1 (initiate the 2nd transfer)
5. Write 0x04 to the highest byte in SPIDAT1 (use WDELAY)
6. Write the 3rd data byte to the lowest byte in SPIDAT1 (initiate the 3rd transfer)

The result : SPI transfer did not work as expected.

Then I have tried the following:

1. Write 0x14 to the highest byte in SPIDAT1
2. Write the first data byte to the lowest byte in SPIDAT1 (initiate the first transfer)
3. Write 0x14 to the highest byte in SPIDAT1
4. Write the second data byte to the lowest byte in SPIDAT1 (initiate the 2nd transfer)
5. Write 0x04 to the highest byte in SPIDAT1 (use WDELAY)
6. Write the 3rd data byte to the lowest byte in SPIDAT1 (initiate the 3rd transfer)

Result: SPI transfer most of the time looks ok. But sometimes the CSn does not work as expected (please see picture)
C1: CSn
C2: SCLK
C3: Data



The manual (spruh79A, chapter 28) does not tell any problems or notes about that behaviour. If I write 32Bit to SPIDAT1 the result is ok. But with EDMA3 only byte writes are possible (?).

Is there any easy solution to this problem? Any known Silicon problems?

Thanks.
Best regards,
Patrick

  • 0
    Genius 4965 points

    Does anyone from TI has an idea?

    Thanks.

    Best regards,

    Patrick

  • 0
    Guru 26430 points

    Not quite sure what the internal bus width is on a 6748. I get the feeling that for SPI controller, it is 16-bits. Maybe a read-modify-write of 8-bit on a 16-bit bus is messing up the SPI controller.

    No expert on DMA. Perhaps you should take a look at the StarterWare SPI EDMA example. That example asserts and deasserts CS outside the DMA transfer itself. The transfer is done 8-bits at a time. It seems like a lot of code to send 3 bytes. A non-DMA PIO approach might be quicker.

    In theory, 32-bit DMA should be possible by setting aCnt to 4. The source buffer would be an array fo SPIDAT1 values. Bigger memory usage as it uses 4 bytes for every data byte But you should be able to send more than one 24-bit value for each DMA burst.