Copy code from DDR into L1P SARAM

Patrick Ruf

Hello,

We are using the C6748 device and CCS V5 with Code Generation Tools V7.3.8. Target: C6748 LCDK
I would like to cut L1P memory in two halfs: lower range for SARAM (for fast algos) higher range for L1P cache.
I do the following:
1. System reset
2. Disconnect target
3. Connect target (--> GEL file initializes DDR and PLL's)
4. Load my code with "Load program..."

Now I can see that L1PMODE is set to 4 (32K for cache) . I have tried a lot of ways to copy my code into the lower section of L1P memory. In vain so far.
The last try was to use "copy_in". With this the code compiled and linked but no copy occured.
Can someone tell me what steps I have to do at the start of my code to get the code copy work?

At this time my code looks like this:

void main(void)
{
CacheDisableMAR((unsigned int)0xC0000000, 0x08000000);

// Enable Cache
CacheEnable(L1PCFG_L1PMODE_16K | L1DCFG_L1DMODE_32K | L2CFG_L2MODE_256K);

// Kopieren des Code Blocks, welcher im L1P SARAM ausgeführt werden muss
copy_in(&text_ZeroWait_copy_table);

// MAR Bits setzen um den Cache für DDR RAM freigeben
CacheEnableMAR((unsigned int)0xC0000000, 0x08000000);

linker cmd file looks like this:

L1P: o = 0x11E00000 l = 0x00008000
L1D: o = 0x11F00000 l = 0x00008000
L2: o = 0x11800000 l = 0x00040000
DDR2: o = 0xC0000000 l = 0x08000000

.text_ZeroWait : LOAD=DDR2, table (_text_ZeroWait_copy_table),
RUN=L1P

Thanks
Best regards,
Patrick

over 12 years ago

0 Julxhino Gocllari over 12 years ago

Prodigy 105 points

Hi Patrick,

I'm not sure if this is going to answer your question, but I think you can't do what you are trying to do. The reason for that is because cache is not like regular memory where you can copy contents where ever you want. Cache is organized completely differently than regular memory. In direct mapped cache, as in the case of the C6748, each line in the cache has a eight 32-bit words (total of 256 bits), and each line has a tag and a dirty bit, from what I remember... Whenever you try to access a memory location, the processor first checks the least significant bits of the address, if it cant find those, it fills up the line, if it does find the LSbits, then it checks the tag, if the tag matches, you have a hit, if it doesn't you have a miss and you fill the line again.

I'm not sure if that helped or not, but I'm pretty sure you can find more info on the net on direct mapped cache memory

Julxhino

0 Patrick Ruf over 12 years ago in reply to Julxhino Gocllari

Genius 4965 points

Hi Julxhino,

Thanks for the reply. L1P memory is dividable into cache and SARAM. In my case the memory is divided by 2 into two 16K blocks (CacheEnable(...). All the applications and reference manuals show this but do not give a real example on how to load code into the SARAM portion (or I did not find it).
Because L1P memory is configured as 32K cache after system reset the "Load program..." can not load my code portion to the memory. Therefore one can not just map the section to L1P in the linker cmd file. One has to copy it after configuration of L1P into cache and SARAM region (in my case 16K + 16K). Unfortunately this does not work in the way I did it.

The question is how to do it the right way?

Patrick

0 Jakez over 12 years ago in reply to Patrick Ruf

Expert 1950 points

Hello Patrick,

The only way to move data into L1PRAM is through IDMA (other masters have no access to program space) from megamodule local SRAM only (L1D or L2D).

However, with CCS you can load code directly into L1P, but you'll have to configure L1P RAM/cache before program loading (and you must then have same RUN and LOAD addresses of L1P code in linker file). You may modify your GEL file, with for example:

OnPreFileLoaded() /* called by CCS before program loading (and after reset, inits,...) */

{ *(int*)0x01840020 = 0; /* L1P as full RAM */ }

You can still configure L1P cache at program beginning.

(This worked with old CCS3.3 and C6455; I suppose CCS5 is still able to)

Jakez

0 Patrick Ruf over 12 years ago in reply to Jakez

Genius 4965 points

Hi Jakez

Thanks a lot for your answer. I appreciate it.

I now try to do the copy with IDMA.

Thanks and best regards,
Patrick

0 Patrick Ruf over 12 years ago in reply to Patrick Ruf

Genius 4965 points

Hello,

Maybe TI can give an answer to this:

I now do a code copy from L2 to L1P using IDMA.

1. Qustion: Is it possible to have a section in the linker command file that loads code into L2? Is it always true that if my code starts (i.e. main()) the L2 is all set to SARAM (what does the bootloader)?
Like this:

L1P: o = 0x11E00000 l = 0x00008000
L2: o = 0x11800000 l = 0x00040000

.text_ZeroWait : LOAD=L2, table (_text_ZeroWait_copy_table),
RUN=L1P

2. Question: Are there any official IDMA register definition in the StarterWare or else where? I have only found "SOC_IDMA_0_REGS". I like to replace the 0x108 for example with a constant:

HWREG(SOC_IDMA_0_REGS+0x108)=text_ZeroWait_copy_table.recs[0].load_addr;
HWREG(SOC_IDMA_0_REGS+0x10C)=text_ZeroWait_copy_table.recs[0].run_addr;
HWREG(SOC_IDMA_0_REGS+0x110)=((7<<29)| (0<<28) | text_ZeroWait_copy_table.recs[0].size);

3. Question: Are there any real code examples that show how to copy code from DDR into L2 or L1P?

Thanks.

Best regards,

Patrick

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Copy code from DDR into L1P SARAM