I am trying to port some code to the beagleboard xM. The code I am porting uses STREX/LDREX and uses the MMU. LDREX/STREX work before I enable the MMU, but once it is enabled those instructions stop working. They seem to give a data abort exception.
Is there a specific configuration I need to perform on the coprocessor that will allow these instructions to work after the MMU is enabled?
code:
#define TTB_S (1 << 1)
#define TTB_RGN_NC (0 << 3)
#define TTB_RGN_OC_WBWA (1 << 3)
#define TTB_RGN_OC_WT (2 << 3)
#define TTB_RGN_OC_WB (3 << 3)
#define TTB_NOS (1 << 5)
#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
#define CPACC_FULL(n) (3 << (n * 2))
#define CPACC_SVC(n) (1 << (n * 2))
#define CPACC_DISABLE(n) (0 << (n * 2))
.type text, %function
ENTRY(text)
msr cpsr_c, #(PSR_F_BIT | PSR_I_BIT | PSR_MODE_SVC)
adr r1, __SRA_INFO
str r0, [r1, #0]
adr r1, text
ldr r2, =(MEMMAP_HYPERVISOR_BASE + 0x8000)
mov r5, r2
mov r3, #0x200000 @ Code size
/* clear page table area */
ttb_setup:
adr r0, text
mov r1, r0
sub r0, r0, #0x4000
mov r2, #0
1: str r2, [r1, #-4]!
str r2, [r1, #-4]!
str r2, [r1, #-4]!
str r2, [r1, #-4]!
cmp r0, r1
bne 1b
adr r4, mem_map_table
b 2f
1:
str r3, [r0, r2]
add r2, r2, #4
add r3, r3, #0x100000
adds r1, r1, #-1
bhi 1b
2:
ldmia r4!, {r1, r2, r3}
cmp r1, #0
bne 1b
/*
#ifdef CONFIG_SMP
mrc p15, 0, r5, c1, c0, 1 @ read aux control register
orr r5, r5, #(1 << 6) | (1 << 0) @ enable SMP/nAMP mode
mcr p15, 0, r5, c1, c0, 1 @ write aux control register
#endif
*/
// Enable L2 Cache
mrc p15, 0, r5, c1, c0, 1 @ read aux control register
orr r5, r5, #(1 << 1) | (1 << 5) @ enable L2 cache
mcr p15, 0, r5, c1, c0, 1 @ write aux control register
orr r0, r0, #TTB_FLAGS @ for WBWA/S
mcr p15, 0, r0, c2, c0, 0 @ Load TTB0
mcr p15, 0, r0, c2, c0, 1 @ Load TTB1
@ TTBCR Setting
mrc p15, 0, r5, c1, c0, 2
orr r5,r5, #((3 << (10 * 2)) |(3 << (11 * 2)))
mcr p15, 0, r5, c1, c0, 2
ldr r5, =0xff0a89a8
ldr r6, =0x40e040e0
mcr p15, 0, r5, c10, c2, 0 @ write PRRR
mcr p15, 0, r6, c10, c2, 1 @ write NMRR
dac_setup:
mov r5, #(DOMAIN_VALUE(DOMAIN_SUPERVISOR, DOMAIN_MANAGER) | \
DOMAIN_VALUE(DOMAIN_HYPERVISOR, DOMAIN_MANAGER) | \
DOMAIN_VALUE(DOMAIN_USER, DOMAIN_MANAGER) | \
DOMAIN_VALUE(DOMAIN_IO, DOMAIN_CLIENT))
mcr p15, 0, r5, c3, c0, 0 @ Load DAC
adr r5, v7_crval
ldmia r5, {r5, r6}
mrc p15, 0, r0, c1, c0, 0 @ read control register
bic r0, r0, r5 @ clear bits them
orr r0, r0, r6 @ set them
#ifdef CONFIG_USE_HIGH_VECTORS
orr r0, r0, #CR_V
#else
bic r0, r0, #CR_V
#endif
mcr p15, 0, r0, c1, c0, 0 @ Turn on MMU
mov r0, r0
mov r0, r0
mov r0, r0
ldr r8, =0x9AF10000
ldr r9, =0xDEADBEEF
1: ldrex r7, [r8] @ <----------------------------- Crashes Here
mov r10, r7
strex r7, r9, [r8]
mov ip, #0
mcr p15, 0, ip, c8, c7, 0 @ Invalidate I, D TLBs
dsb
isb
b clear_bss
/* AT
* TFR EV X F I D LR S
* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
* 1 0 110 0011 1100 .111 1101 < we want
*/
.type v7_crval, #object
v7_crval:
.long 0x0120c302
.long 0x10c03c7d
Thanks,
Robbie VanVossen
