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Ignorant cache question in Msgq

Kent Dekome
Intellectual 630 points

Using a shared region to pass data between cores and am running into what I believe is a caching issue...

DSP: sets *ptr = -3 then sends ptr to ARM via MsgQ

ARM:  sets *ptr = -2

DSP: waits on *ptr = -2 and then sets *ptr = -1

ARM: waits on *ptr = -1 and then sets *ptr = 0

If I leave DSP caching enabled DSP sees the *ptr = -2 but ARM never sees *ptr = -1

If I use

Cache_setMar( (void *)ptr, 4, Cache_Mar_DISABLE );

on DSP side DSP never sees *ptr = -2 as set by ARM...

Whats going on here?

  • 0
    Intellectual 630 points

    Well you shouldnt have moved this to Linux forum since I am currently doing both cores in sys/bios to debug the algo.

    I've got the shared memory synched up on both cores by using Cache_inv() and Cache_wb() as necessary on both cores...

    I guess I'm at a loss right now to explain why

    Cache_setMar( (void *)ptr, 4, Cache_Mar_DISABLE );

    as mentioned above did not seem to affect the use of the cache...

  • 0 in reply to Kent Dekome
    TI__Guru 59700 points

    Are you using ipc from TI for sending msgs or is it your own implementation. The reason is ipc takes care of cache coherency and if you are seeing this issue then it is a bug or a configuration issue.

    If you are working on your own implementation the following should be considered.

    1. Shared memory pointers should be aligned to cache line (128 bytes on DSP).This is because granularity of cache operation is cache line.

    2. You need to have a multi processor gate ensuring excluive access before doing any operation on the shared memory pointer.

        - Multiprocessor gate should  guarantee exclusive access on same processor and remote processor.

        - You can refer ipc/packages/ti/sdo/ipc/gates/GatePeterson.c for reference implementation.

    3. As you have indicated, you need to do Cache_wb after write and Cache_inv before reading the shared memory pointer.

    As to why Cache_setMar doesnt work :

    -- This will disable caching on DSP. How are you disabling caching on ARM ?

    -- Also are you disabling MAR bits initially before shared memory access on DSP . Setting MAR bits affects further reads and writes. I dont think it will flush cache if content is already present in cache line.