Hi,
I've read from TRM that video input ports(VIP 0, VIP 1) of DM814x can support upto 165MHz of incoming pixel clock frequency.
I've a source which provides BT656 output and it is connected DM814x VIN0 portA [7:0]. The details are listed below.
Input to DM814x VIN0_portA [7:0]
Pixel clock freq --> 28.375 MHz.
Data format : 8 bit embedded sync single 4:2:2 YUV stream
Resolution Information(from source): 582 x 752
The VIP input register configurations are:
0ffset: 0x0 (main Register Format ) : 0x2
Offset: 0x4 (port_a Register Format) : 0x500
The status register value observed is,
Offset: 0x1C (fiq_status Register Format) : 0x34404
which means, Port A ANC VPI Protocol Violation FIQ bit is set, Port A YUV VPI Protocol Violation FIQ is set, Port A Unexpected Size Status bit is set, VDET Status for Port A is not set, Port A Link Connect Status is set.
So, resolution is not getting latched in the VIP parser of DM814x for this PCLK frequency. output_port_a_src0_size Register reads 0x0. But We have tested this source output by giving it Sil9022A (HDMI transmitter) by doing custom wiring. we are able to get the input video on HDMI monitor.
Also, If I give data at the standard pixel clock frequency of 27MHz to VIP of DM814x, I can see the resolution getting latched. What needs to be done to capture video at 28.375MHz?? Why the status registers say as violation of VPI protocol??
Thanks and regards,
Vaishnavi
