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EMIF CECTL register for asyn Memory!

Ouahid
Prodigy 10 points

I am looking for a solution for my project.

The DSP C6713B is used to transfer data to 2 FPGAs: the 2 FPGAs use the same EMIF Interface, for FPGA1 D[31:0] lines are used and for FPGA2 only D[7:0] lines are used. The 2 FPGAs are 32-Bit devices.

I can configure the memory type in field MTYPE in regsiter CECTL to select the ASYNC mode.

My question is: is it possible to modify the field MTYPE for asyn interface in the register CECTL after start up and initialization phase and during operation?  I want to read/write from/to both FPGAs, one time with 8-Bit-wide and one time with 32-Bit-wide.

Thanks!

Ouahid

  • 0
    TI__Guru*** 125430 points

    Ouahid said:
    The DSP C6713B is used to transfer data to 2 FPGAs: the 2 FPGAs use the same EMIF Interface, for FPGA1 D[31:0] lines are used and for FPGA2 only D[7:0] lines are used. The 2 FPGAs are 32-Bit devices.

    The EMIF is designed to be a shared bus, i.e. multiple slave devices hanging off.  For that reason we have multiple chip selects.  Did you connect a unique chip select to each of your FPGAs?  If so, you should be able to independently program each corresponding chip select space.  In other words, the intent is that you would connect a unique chip select to each device and then program the corresponding CECTL register for the appropriate width.