Hello.
I need to connect OMAP3530 processor to IOM-2 bus using McBSP. For the correct IOM-2 bus execution CLK with 4.096Mhz frequency and Frame Sync with 8Khz frequency have to be generated (every 512 cycles). To achieve this, I've connected generator with 8.192Mhz frequency to McBSP_CLKS input and set divider SRGR1_CLKDV=3.
Cycles are generated properly, but CLK glorks as data yields from McBSP3_DX, to wit when transition from Hi level to Low Level occurs (see pic.)
I wonder if you'd tell me why this happens and if it is real to execute a transmission with 4.096 frequency. This frequency can't be collated using divider.
