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c6657 DDR Configuration Table during Ethernet Boot

Other Parts Discussed in Thread: TMS320C6657

Hi all,

As mentioned in sprugy5b there is a DDR configuration table that can be used to set up external memory during a boot.  My questions are whether this functionality is available during the Ethernet Boot mode for the TMS320C6657 (the main goal is to configure the DDR and load the program into DDR without using any secondary boot loaders), and if it is, where in the L2 memory is the table located during the boot process?

I also noticed that the c6657 technical data sheet (sprs814a) mentions that the starting address for the section of the L2 SRAM that the boot loader uses is 0x00872DC0, is this correct or should it be 0x008F2DC0?

Thanks,

Mark

  • Any update on this? I just want to know if it is possible to use the DDR Configuration table as described in the bullet point before Table 2-3 of sprugy5b during an Ethernet Boot (without any other boot modes before it).

    I am curious becuase when I look at the L2 memory locations where the DDR configuration table would be during an Ethernet boot (i.e. when the BOOTP packets are being broadcast), the memory is not all zeroes like decribed in the bullet point mentioned above.

    Any insight would be greatly appreciated.

    Mark

  • Mark,

    I'm having trouble finding the reference to 0x8f2dc0 that's causing confusion...can you clarify the location in the documentation thats causing the conflicting data?

    And just out of curiousity, did you you look in both memory locations for the DDR2 initializaiton to zeros?

     

  • Dave,

    For the c6657 there is no mention of 0x8f2dc0 as the starting address of L2 memory usage by the RBL.  The main reason I think that the starting address is 0x8f2dc0 instead of the 0x872dc0 mentioned in section 2.4 of SPRS814A, is becuase if I connect using CCS when the DSP is broadcasting the BOOTP packets and look at the memory, 0x8FFFFC is where the Boot Magic Address is eventually put, say if you load simple.eth provided with the mcsdk.  I also notice other areas between 0x8f2dc0-0x8FFFFF are populated with the sections described in Table 2-2 of SPRUGY5B, while 0x872dc0-0x87FFFF remain random values.

    To answer your other question, yes I have checked both 0x873500 (0x872dc0+0x740) and 0x8F3500 (0x8f2dc0+0x740) and they are not zeroed during the Ethernet boot process.

    Thanks for looking into this,

    Mark

  • Sorry if it wasn't clear from the last post, but I am still waiting on any answers for this.  Am I even looking in the right area, or is my understanding of the what is available when the DSP is broadcasting BOOTP packets just wrong?

    Any input would be greatly appreciated,

    Mark

  • Sorry for the delay. Yes you can do that. The DDR table structure is in the attached document. I have also added the location of the structure in the L2. Please let me know if this works.

    Thanks,

    Arun.4466.DRR_Configuration_for_C6657.docx

  • Also the main reason it is different that the one in the user guide, was that the configuration table s for C667x devices and we haven't updated it for the C665x.

    Thanks,

    Arun.

  • Hi Arun,

    Thanks for the response that helped a great deal.  I noticed during testing that it looks like the DDR3 PLL configuration is actually split into three 32-bit values (at byte offset 12, 16, and 20).  The 32-bit value at byte offset 12 is the PLLD value (number loaded is actually set value-1) that is loaded into bits_0:5 of DDR3PLLCTL0.  The 32-bit value at byte offset 16 is the PLLM value (number loaded is actually set value-1)  that is loaded into bits_6:18 of DDR3PLLCTL0.  The 32-bit section at byte offset  20 I assume is the PREDIV value (which should always be set to 2?).   Making those changes I was able to configure the DDR3 with a single .eth file loaded with the Ethernet Boot mode.

    My ,hopefully, last question is whether the fix for Advisory 3 of the errata (SPRZ381) is implemented in the DDR configuration routine used by the RBL, or is it not an issue becuase the RBL does not use automatic leveling?

    Thanks for the continued assistance,

    Mark

  • Hi all,

    I would add a little question about the ethernet boot.

    I'm tryng the eth boot on the c6657evm and I have some problems that I don't understand.

    1) I followed the procedure written in the "simple" example and the DSP doesn't start, but it continues to send the bootp paket (attached)

    I think that the output packet iscorrect (proocols, MAC, cksums, IP addresses, boot table frame headers, payload data multiple of 4 bytes in length) 

    "ti\mcsdk_2_01_01_04\tools\boot_loader\examples\ethernet\docs"

    ROM Ethernet boot example

    A simple example demonstrating ROM Ethernet boot.

    Steps to build the example:

    1. Run "simple.bat" under "tools\boot_loader\examples\ethernet\simple\". This will build the simple.out and use
    hex6x.exe (delivered in CG tools package) to convert the .out to a boot table file, and then use the
    bconvert64x.exe/bootpacket.exe to convert the hex6x boot table file to the Ethernet boot format data file,
    simple.eth. "Simple .bat is a little strange

    I rewrote it in this mode without recompiling simple.s ( simple.out with the emulator it runs correctly)


    C:\ti\ccsv5\tools\compiler\c6000\bin\hex6x simple.rmd
    ..\Utilities\bconvert64x -le simple.btbl simple.le.btbl
    ..\Utilities\bootpacket simple.le.btbl simple.eth
    copy simple.eth ..\Ethernet_boot\simple.eth

    Steps to send the simple.eth from the Host to the target DSP

    1. Boot the target DSP in ROM Ethernet boot mode. 

    The DIP switch setting for C6657 EVM is:

    SW3(pin1, pin2, pin3, pin4, pin5, pin6, pin7, pin8): off, on, off, on, on, on, on, off  
    SW5(pin1, pin2, pin3, pin4, pin5, pin6, pin7, pin8): on, off, on, off, off, on, on, on

    2. Once the DSP boots up, it transmits BOOTP packet at regular interval which will have the MAC ID of the DSP. OK

    3. Add an ARP entry for the DSP MAC address associating with an IP local to the host. For example if the host PC's
    IP is 192.168.1.1, then add an ARP entry with the DSP's MAC address associated with IP address 192.168.1.2. OK

    4. Use the pcsendpkt.exe to send the image to the DSP using the associated IP address. For example
    pcsendpkt.exe simple.eth 192.168.1.2 OK

    5. Use CCS to connect the EVM, and check that A1 register is set to 0x11223344, that confirms the simple program
    is received and booted by the ROM boot loader. "DSP DOES NOT START"

    2) Moreover I tried to create a DSP boot IMAGE starting to the .out of  the example project  "i2ctftpboot_evmc6657l" (hello world on UART)

    but the hex6x option are worng and the execution go in error. 

    \ti\ccsv5\tools\compiler\c6000\bin\hex6x -a -e _cint00 -order L  i2ctftpboot_evmc6657l.out

    Can you direct me to a possible solution?

    thank you very much

    Max

  • Hi Max,

    If I am understanding your description correctly, you are able to see the BOOTP packets, set up the arp table and then send the .eth file over but the DSP does not receive it.  I think the problem is the EMAC Boot issue mentioned here: http://www.einfochips.com/TI/C6657%20Lite%20EVM%20Known%20Issues.pdf.

    Hope that helps,

    Mark

  • It Works perfectly!

    thank you Mark!

    And for the second question? Have yo tried to bulid an image for DSP more big than simple.eth?  :- ) 

  • Hi Mark,

    have you ever used hex6x for build a eth boot image?

    My goal is to create a custom IBL booted by Ethernet RBL.

    But I have some problems to load a program like this simple example C:\ti\mcsdk_2_01_01_04\examples\ndk\client\evmc6657l\Debug\evmc6657l.out

    The DSP seems jump to the entry point but it doesn't work.

    do you have any suggestions?

    Thank you

     

  • Hi Arun,

    I am trying to do Ethboot on C6670 EVM. 

    I could succeed in loading the simple.eth provided along with MCSDK and verified that A1 register contains 0x11223344 using the emulator.

    For my actual application, LTE stack, I need to load the image in DDR for which I need to configure the DDR before loading the boot image.

    From this thread, I understand that configuring the DDR using Boot configuration table is POSSIBLE without secondary boot loader.

    But I could not get any information on how to achieve that.  My queries are,

    1. How to create the DDR configuration table to be loadable along with boot image?  (The document given by you in link provides list of registers that I need to configure. But where to put values for those registers? Should I form a text file or a c function intializing a structure of registers with these values, but where to invoke that c function?)

    2. How to combine the created DDR configuration table with the boot image? (so that it will become single boot image)

    Thanks in advance.

    With Regards,

    - Gopi