DM8168 DVR RDK decode and display lag

/*
 *  Copyright (c) 2010-2011, Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *  *  Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *
 *  *  Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *
 *  *  Neither the name of Texas Instruments Incorporated nor the names of
 *     its contributors may be used to endorse or promote products derived
 *     from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 *  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 *  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 *  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 *  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 *  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 *  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 *  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 *  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 *  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  Contact information for paper mail:
 *  Texas Instruments
 *  Post Office Box 655303
 *  Dallas, Texas 75265
 *  Contact information:
 *  http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm?
 *  DCMP=TIHomeTracking&HQS=Other+OT+home_d_contact
 *  ============================================================================
 *
 */

#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <signal.h>
#include <fcntl.h>
#include <ctype.h>
#include <termios.h>
#include <sys/types.h>
#include <sys/mman.h>

#define DISPLAY_STR(str)  printf (str);
#define DISPLAY_STR2(str, x, y) printf (str, x, y);

#define GEL_TextOut(mstr, sstr, x, y, z) printf ( "CortxA8: Output:    " mstr,z);

#define DISP_ADDRPHY_ADDRVIRT_DATA(x, y, z) printf ("             " "Phy Addr : 0x%0.8x Data : 0x%0.8x\n", x,  z);
#define DISP_ADDRPHY_ADDRVIRT_DATA_BW(x, y, z) printf ("             " "BW Phy Addr : 0x%0.8x Data : 0x%0.8x\n", x,  z);
#define DISP_ADDRPHY_ADDRVIRT_DATA_AW(x, y, z) printf ("             " "AW Phy Addr : 0x%0.8x Data : 0x%0.8x\n", x,  z);

#define MAP_SIZE (1024*1024)
#define MAP_MASK (MAP_SIZE-1)

#define PM_ACTIVE_PWRSTCTRL			0x48180A00
#define PM_DEFAULT_PWRSTCTRL			0x48180B00
#define PM_IVAHD0_PWRSTCTRL			0x48180C00
#define PM_IVAHD1_PWRSTCTRL			0x48180D00
#define PM_IVAHD2_PWRSTCTRL			0x48180E00
#define PM_SGX_PWRSTCTRL			0x48180F00

#define CM_GEM_CLKCTRL				0x48180400
#define CM_HDDSS_CLKCTRL			0x48180404
#define CM_HDMI_CLKCTRL				0x48180408
#define CM_ACTIVE_GEM_CLKCTRL			0x48180420
#define CM_ACTIVE_HDDSS_CLKCTRL			0x48180424
#define CM_ACTIVE_HDMI_CLKCTRL			0x48180428

#define CM_DEFAULT_L3_MED_CLKSTCTRL		0x48180504
#define CM_DEFAULT_L3_FAST_CLKSTCTRL		0x48180508
#define CM_DEFAULT_PCI_CLKSTCTRL		0x48180510
#define CM_DEFAULT_L3_SLOW_CLKSTCTRL		0x48180514
#define CM_DEFAULT_CLKSTCTRL 			0x48180518
#define CM_DEFAULT_EMIF_0_CLKCTRL		0x48180520
#define CM_DEFAULT_EMIF_1_CLKCTRL		0x48180524
#define CM_DEFAULT_DMM_CLKCTRL			0x48180528
#define CM_DEFAULT_FW_CLKCTRL 			0x4818052C
#define CM_DEFAULT_USB_CLKCTRL 			0x48180558
#define CM_DEFAULT_SATA_CLKCTRL 		0x48180560
#define CM_DEFAULT_PCI_CLKCTRL  		0x48180578

#define CM_IVAHD0_CLKCTRL	 		0x48180600
#define CM_IVAHD0_IVAHD_CLKCTRL 		0x48180620
#define CM_IVAHD0_SL2_CLKCTRL	 		0x48180624

#define CM_IVAHD1_CLKCTRL	 		0x48180700
#define CM_IVAHD1_IVAHD_CLKCTRL 		0x48180720
#define CM_IVAHD1_SL2_CLKCTRL	 		0x48180724

#define CM_IVAHD2_CLKCTRL	 		0x48180800
#define CM_IVAHD2_IVAHD_CLKCTRL 		0x48180820
#define CM_IVAHD2_SL2_CLKCTRL	 		0x48180824

#define CM_SGX_CLKSTCTRL			0x48180900
#define CM_SGX_SGX_CLKCTRL	 		0x48180920

#define MAINPLL_CTRL		0x48140400
#define MAINPLL_FREQ1		0x48140408
#define MAINPLL_DIV1		0x4814040C
#define MAINPLL_FREQ2		0x48140410
#define MAINPLL_DIV2		0x48140414
#define MAINPLL_FREQ3		0x48140418
#define MAINPLL_DIV3		0x4814041C
#define MAINPLL_FREQ4		0x48140420
#define MAINPLL_DIV4		0x48140424
#define MAINPLL_FREQ5		0x48140428
#define MAINPLL_DIV5		0x4814042C
#define MAINPLL_DIV6		0x48140434
#define MAINPLL_DIV7		0x4814043C

#define DDRPLL_CTRL		0x48140440
#define DDRPLL_DIV1		0x4814044C
#define DDRPLL_FREQ2		0x48140450
#define DDRPLL_DIV2		0x48140454
#define DDRPLL_FREQ3		0x48140458
#define DDRPLL_DIV3		0x4814045C
#define DDRPLL_FREQ4		0x48140460
#define DDRPLL_DIV4		0x48140464
#define DDRPLL_FREQ5		0x48140468
#define DDRPLL_DIV5		0x4814046C

#define VIDEOPLL_CTRL		0x48140470
#define VIDEOPLL_FREQ1		0x48140478
#define VIDEOPLL_DIV1		0x4814047C
#define VIDEOPLL_FREQ2		0x48140480
#define VIDEOPLL_DIV2		0x48140484
#define VIDEOPLL_FREQ3		0x48140488
#define VIDEOPLL_DIV3		0x4814048C

#define AUDIOPLL_CTRL		0x481404A0
#define AUDIOPLL_FREQ2		0x481404B0
#define AUDIOPLL_DIV2		0x481404B4
#define AUDIOPLL_FREQ3		0x481404B8
#define AUDIOPLL_DIV3		0x481404BC
#define AUDIOPLL_FREQ4		0x481404C0
#define AUDIOPLL_DIV4		0x481404C4
#define AUDIOPLL_FREQ5		0x481404C8
#define AUDIOPLL_DIV5		0x481404CC

#define CM_SYSCLK1_CLKSEL       0x48180300
#define CM_SYSCLK2_CLKSEL       0x48180304
#define CM_SYSCLK3_CLKSEL       0x48180308
#define CM_SYSCLK4_CLKSEL       0x4818030C
#define CM_SYSCLK5_CLKSEL       0x48180310
#define CM_SYSCLK6_CLKSEL       0x48180314
#define CM_SYSCLK7_CLKSEL       0x48180318
#define CM_SYSCLK10_CLKSEL      0x48180324
#define CM_SYSCLK11_CLKSEL      0x4818032C
#define CM_SYSCLK13_CLKSEL      0x48180334
#define CM_SYSCLK15_CLKSEL      0x48180338
#define CM_SYSCLK19_CLKSEL      0x4818034C
#define CM_SYSCLK20_CLKSEL      0x48180350
#define CM_SYSCLK21_CLKSEL      0x48180354
#define CM_SYSCLK22_CLKSEL      0x48180358
#define CM_SYSCLK23_CLKSEL      0x481803B0
#define CM_SYSCLK24_CLKSEL      0x481803B4
#define CM_VPB3_CLKSEL		0x48180340
#define CM_VPC1_CLKSEL		0x48180344
#define CM_VPD1_CLKSEL		0x48180348
#define CM_SYSCLK14_CLKSEL      0x48180370
#define CM_SYSCLK16_CLKSEL      0x48180374
#define CM_SYSCLK18_CLKSEL      0x48180378
#define CM_AUDIOCLK_MCASP0_CLKSEL          0x4818037C
#define CM_AUDIOCLK_MCASP1_CLKSEL          0x48180380
#define CM_AUDIOCLK_MCASP2_CLKSEL          0x48180384
#define CM_AUDIOCLK_MCBSP_CLKSEL           0x48180388

void WR_MEM_32(unsigned int addr, unsigned int data);
unsigned int RD_MEM_32(unsigned int addr);

int CLKIN =	27;

volatile unsigned int *virt_addr;
int us_fd;

void WR_MEM_32(unsigned int addr, unsigned int data)
{
	void *map_base;
	unsigned int data_bs;
	unsigned int data_as;
	unsigned int size;
	off_t target;

	target = addr;
	size = 4;

	/* Map one page */
	map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, us_fd, target & ~MAP_MASK);
	if(map_base == (void *) -1){
		printf ("Could not open the mem file \n");
	}
	printf("data %x\n", data);
	virt_addr = (unsigned int *)(map_base + (target & MAP_MASK));
	data_bs = *virt_addr;
	*virt_addr = data;
	data_as = *virt_addr;

	DISP_ADDRPHY_ADDRVIRT_DATA_BW(target, virt_addr, data_bs);
	DISP_ADDRPHY_ADDRVIRT_DATA_AW(target, virt_addr, data_as);

	munmap(map_base,/*MAP_SIZE */ MAP_SIZE);
}

unsigned int RD_MEM_32(unsigned int addr)
{
	void *map_base;
	unsigned int data;
	unsigned int data_as;
	unsigned int size;
	off_t target;

	target = addr;
	size = 4;

	/* Map one page */
	map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, us_fd, target & ~MAP_MASK);
	if(map_base == (void *) -1) {
		printf ("Could not open the mem file \n");
	}
	virt_addr = (unsigned int*)(map_base + (target & MAP_MASK));
	data = *virt_addr;
	DISP_ADDRPHY_ADDRVIRT_DATA(target, virt_addr, data);

	munmap(map_base,/*MAP_SIZE */ MAP_SIZE);

	return data;
}

void get_powerstate(unsigned int addr)
{
	unsigned int data;
	int powerstate;
	
	data = RD_MEM_32(addr);
	powerstate = data & 0x3u;
	if (powerstate == 0x0u)
		printf("POWERSTATE: %d, OFF State\n\n",powerstate);
	else if (powerstate == 0x3u)
		printf("POWERSTATE: %d, ON State\n\n",powerstate);
}

void get_clocktrctrl(unsigned int addr)
{
	unsigned int data;
	int clocktrctrl;
	
	data = RD_MEM_32(addr);
	clocktrctrl = data & 0x3u;
	if (clocktrctrl == 0x1u)
		printf("CLOCKTRCTRL: %d, SW_SLEEP\n\n",clocktrctrl);
	else if (clocktrctrl == 0x2u)
		printf("CLOCKTRCTRL: %d, SW_WKUP\n\n",clocktrctrl);
}

void get_modulemode(unsigned int addr)
{
	unsigned int data;
	int moduleMode;
	
	data = RD_MEM_32(addr);
	moduleMode = data & 0x3u;
	if (moduleMode == 0x2u)
		printf("MODULEMODE: %d, MODULE ENABLED\n\n",moduleMode);
	else if (moduleMode == 0x0u)
		printf("MODULEMODE: %d, MODULE DISABLED\n\n",moduleMode);
}

void get_powerInfo()
{
	printf("\n*************************ACTIVE DOMAIN**********************\n");
	printf("ACTIVE Power State:\n");
	get_powerstate(PM_ACTIVE_PWRSTCTRL);
	printf("DSP Clock Domain Power State:\n");
	get_clocktrctrl(CM_GEM_CLKCTRL);
	printf("DSP Clock:\n");
	get_modulemode(CM_ACTIVE_GEM_CLKCTRL);
	printf("HDVPSS Clock Domain Power state:\n");
	get_clocktrctrl(CM_HDDSS_CLKCTRL);
	printf("HDVPSS Clock:\n");
	get_modulemode(CM_ACTIVE_HDDSS_CLKCTRL);
	printf("HDMI Clock Domain Power State\n");
	get_clocktrctrl(CM_HDMI_CLKCTRL);
	printf("HDMI Clock:\n");
	get_modulemode(CM_ACTIVE_HDMI_CLKCTRL);
	printf("************************************************************\n");
	
	printf("\n***********************DEFAULT DOMAIN***********************\n");
	printf("DEFAULT Power State:\n");
	get_powerstate(PM_DEFAULT_PWRSTCTRL);
	printf("L3 Medium Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_L3_MED_CLKSTCTRL);
	printf("L3 Fast Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_L3_FAST_CLKSTCTRL);
	printf("PCI Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_PCI_CLKSTCTRL);
	printf("L3 Slow Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_L3_SLOW_CLKSTCTRL);
	printf("Default Clock Domain: \n");
	get_clocktrctrl(CM_DEFAULT_CLKSTCTRL);
	printf("EMIF0 Clock:\n");
	get_modulemode(CM_DEFAULT_EMIF_0_CLKCTRL);
	printf("EMIF1 Clock:\n");
	get_modulemode(CM_DEFAULT_EMIF_1_CLKCTRL);
	printf("DMM Clock:\n");
	get_modulemode(CM_DEFAULT_DMM_CLKCTRL);
	printf("EMIF FW Clock:\n");
	get_modulemode(CM_DEFAULT_FW_CLKCTRL);
	printf("USB Clock:\n");
	get_modulemode(CM_DEFAULT_USB_CLKCTRL);
	printf("SATA Clock:\n");
	get_modulemode(CM_DEFAULT_SATA_CLKCTRL);
	printf("PCI Clock:\n");
	get_modulemode(CM_DEFAULT_PCI_CLKCTRL);
	printf("************************************************************\n");
	
	printf("\n***********************IVAHD0 Domain************************\n");
	printf("IVAHD0 Power State:\n");
	get_powerstate(PM_IVAHD0_PWRSTCTRL);
	printf("IVAHD0 Clock Domain Power State:\n");
	get_clocktrctrl(CM_IVAHD0_CLKCTRL);
	printf("HDVICP0 Clock:\n");
	get_modulemode(CM_IVAHD0_IVAHD_CLKCTRL);
	printf("HDVICP0 SL2 Clock:\n");
	get_modulemode(CM_IVAHD0_SL2_CLKCTRL);
	printf("************************************************************\n");

	printf("\n***********************IVAHD1 Domain************************\n");
	printf("IVAHD1 Power State:\n");
	get_powerstate(PM_IVAHD1_PWRSTCTRL);
	printf("IVAHD1 Clock Domain Power State:\n");
	get_clocktrctrl(CM_IVAHD1_CLKCTRL);
	printf("HDVICP1 Clock:\n");
	get_modulemode(CM_IVAHD1_IVAHD_CLKCTRL);
	printf("HDVICP1 SL2 Clock:\n");
	get_modulemode(CM_IVAHD1_SL2_CLKCTRL);
	printf("************************************************************\n");

	printf("\n************************IVAHD2 Domain***********************\n");
	printf("IVAHD2 Power State:\n");
	get_powerstate(PM_IVAHD2_PWRSTCTRL);
	printf("IVAHD2 Clock Domain Power State:\n");
	get_clocktrctrl(CM_IVAHD2_CLKCTRL);
	printf("HDVICP2 Clock:\n");
	get_modulemode(CM_IVAHD2_IVAHD_CLKCTRL);
	printf("HDVICP2 SL2 Clock:\n");
	get_modulemode(CM_IVAHD2_SL2_CLKCTRL);
	printf("************************************************************\n");
	
	printf("\n************************SGX Domain**************************\n");
	printf("SGX Power State:\n");
	get_powerstate(PM_SGX_PWRSTCTRL);
	printf("SGX Clock Domain Power State:\n");
	get_clocktrctrl(CM_SGX_CLKSTCTRL);
	printf("SGX Clock:\n");	
	get_modulemode(CM_SGX_SGX_CLKCTRL);
	printf("************************************************************\n");
}

float readPLL(unsigned int pll_ctrl, unsigned int pll_freq, unsigned int pll_div)
{
	unsigned int mult, div, pre_div, integer, ctrl_reg, freq_reg;
	float frac, freq, value_freq;
	
	ctrl_reg = RD_MEM_32(pll_ctrl);
	if ((ctrl_reg & 0x00000008) == 0x8)
		printf("PLL is enabled\n");
	else
		printf("PLL is disabled\n");

	if ((ctrl_reg & 0x00000004) == 0x4)
		printf("PLL is in normal operation\n");
	else
		printf("PLL is in bypass mode\n");

	freq_reg    = RD_MEM_32(pll_freq);
	mult        = (ctrl_reg & 0xFFFF0000) >> 16;
	pre_div     = (ctrl_reg & 0xFF00)>>8;
	frac        = ((float)(freq_reg & 0xFFFFFF))/ ((float) (0x1000000-1));
	integer     = (freq_reg & 0xF000000) >>24;
	freq        = frac + integer;
	div         = (RD_MEM_32(pll_div) & 0xFF);
	value_freq    = ((float) (27 * mult * 8)) / ((float) ((pre_div * freq) * div));
	return value_freq;
}

void getdivPLL(unsigned int pll_ctrl,unsigned int pll_div)
{
	unsigned int ddr_mult, ddr_div, ddr_pre_div, dmm_int;
	float ddr_freq, dmm_freq, dmm_frac, freq;
	
	ddr_mult    = (RD_MEM_32(pll_ctrl) & 0xFFFF0000)>>16;
	ddr_div     = (RD_MEM_32(pll_div) & 0xFF);
	ddr_pre_div = (RD_MEM_32(pll_ctrl) & 0xFF00)>>8;
	ddr_freq    = (27 * ddr_mult)/(ddr_div * ddr_pre_div);
	printf("\n\nfreq = %f\n", ddr_freq);
}

int main(int argc, char **argv) 
{
	void *map_base;
	unsigned long read_result, writeval;
	unsigned int addr, data;
	int i;

	float freq_sysclk[24], value_freq,  value_freq_B3, value_freq_C1, 
		value_freq_D1, freq_mcasp0, freq_mcasp1, freq_mcasp2, freq_mcbsp;
	int prcm_div[24], prcm_div_B3, prcm_div_C1, prcm_div_D1, 
				mcasp0_clk, mcasp1_clk, mcasp2_clk, mcbsp_clk;
    
	if(argc < 2) {
		printf("Usage: %s [p|f]\n\t p : for module mode\n\t f : for pll frequency",  argv[0]);
		exit(1);
    	}

	if((us_fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
		printf ("Could not open the mem file \n");
	}

	printf("/dev/mem opened.\n");
	switch (argv[1][0]) {
		case 'p':
			printf ("GET PLL Status\n");
			get_powerInfo();
			break;
		case 'f':
			for (i = 0; i < 24; i++)
				prcm_div[i] = -1;

			printf ("PLL Frequency\n");
			printf ("*******************MAINPLL********************\n");

			/* For FREQ1 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ1, MAINPLL_DIV1);
			printf("\nFREQ1 : %f Mhz\n\n",value_freq);
			prcm_div[0] = (RD_MEM_32(CM_SYSCLK1_CLKSEL) & 0x07) + 1;
			freq_sysclk[0] = value_freq / ((float) prcm_div[0]);
			printf("\nSYSCLK1 (DSP)\t: %f Mhz\n\n", freq_sysclk[0]);
			printf("-----------------------------------------------------\n");
			
			/* For FREQ2 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ2, MAINPLL_DIV2);
			printf("\nFREQ2 : %f Mhz\n\n",value_freq);
			prcm_div[1] = (RD_MEM_32(CM_SYSCLK2_CLKSEL) & 0x07) + 1;
			freq_sysclk[1] = value_freq / ((float) prcm_div[1]);
			printf("\nSYSCLK2 (A8)\t: %f Mhz\n\n",freq_sysclk[1]);
			prcm_div[22] = (RD_MEM_32(CM_SYSCLK23_CLKSEL) & 0x07) + 1;
			freq_sysclk[22] = value_freq / ((float) prcm_div[22]);
			printf("\nSYSCLK23 (SGX)\t: %f Mhz\n\n",freq_sysclk[22]);
			printf("-----------------------------------------------------\n");

			/* For FREQ3 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ3, MAINPLL_DIV3);
			printf("\nFREQ3 : %f Mhz\n\n",value_freq);
			prcm_div[2] = (RD_MEM_32(CM_SYSCLK3_CLKSEL) & 0x07) + 1;
			freq_sysclk[2] = value_freq / ((float) prcm_div[2]);
			printf("\nSYSCLK3 (hdvicp2)\t: %f Mhz\n\n",freq_sysclk[2]);
			printf("-----------------------------------------------------\n");

			/* For FREQ4 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ4, MAINPLL_DIV4);
			printf("\nFREQ4 : %f Mhz\n\n",value_freq);
			prcm_div[3] = (RD_MEM_32(CM_SYSCLK4_CLKSEL) & 0x01) + 1;
			freq_sysclk[3] = value_freq / ((float) prcm_div[3]);
			printf("\nSYSCLK4 \t: %f Mhz\n\n",freq_sysclk[3]);
			prcm_div[4] = (RD_MEM_32(CM_SYSCLK5_CLKSEL) & 0x01) + 1;
			freq_sysclk[4] = freq_sysclk[3] / ((float) prcm_div[4]);
			printf("\nSYSCLK5 \t: %f Mhz\n\n", freq_sysclk[4]);
			prcm_div[5] = ((RD_MEM_32(CM_SYSCLK6_CLKSEL) & 0x01) + 1) * 2;
			freq_sysclk[5] = freq_sysclk[3] / ((float) prcm_div[5]);
			printf("\nSYSCLK6 \t: %f Mhz\n\n",freq_sysclk[5]);
			prcm_div[6] = (RD_MEM_32(CM_SYSCLK7_CLKSEL) & 0x03);
			if (prcm_div[6] == 0)
				prcm_div[6] = 5;
			else if (prcm_div[6] == 1)
				prcm_div[6] = 6;
			else if (prcm_div[6] == 2)
				prcm_div[6] = 8;
			else if (prcm_div[6] == 3)
				prcm_div[6] = 16;

			freq_sysclk[6] = freq_sysclk[3] / ((float) prcm_div[6]);
			printf("\nSYSCLK7 \t: %f Mhz\n\n",freq_sysclk[6]);
			printf("-----------------------------------------------------\n");

			/* For FREQ5 */
			value_freq = readPLL(MAINPLL_CTRL, MAINPLL_FREQ5, MAINPLL_DIV5);
			printf("\nFREQ5 : %f Mhz\n\n",value_freq);
			prcm_div[23] = (RD_MEM_32(CM_SYSCLK24_CLKSEL) & 0x07) + 1;
			freq_sysclk[23] = value_freq / ((float) prcm_div[23]);
			printf("\nSYSCLK24 (EMAC)\t: %f Mhz\n\n",freq_sysclk[23]);
			printf("-----------------------------------------------------\n");

			printf("\nUSB Clock\n");
			getdivPLL(MAINPLL_CTRL, MAINPLL_DIV6);
			printf("\nAUDIO PLL Reference clock\n");
			getdivPLL(MAINPLL_CTRL, MAINPLL_DIV7);
			printf("-----------------------------------------------------\n");

			printf ("*******************DDRPLL********************\n");

			/* For FREQ2 */
			value_freq = readPLL(DDRPLL_CTRL, DDRPLL_FREQ2, DDRPLL_DIV2);
			printf("\nFREQ2 : %f Mhz\n\n",value_freq);
			prcm_div[9] = (RD_MEM_32(CM_SYSCLK10_CLKSEL) & 0x01) + 1;
			freq_sysclk[9] = value_freq / ((float) prcm_div[9]);
			printf("\nSYSCLK10 (SPI,I2C,SD,UART): %f Mhz\n\n",freq_sysclk[9]);
			freq_sysclk[8] = freq_sysclk[9] / 3;
			printf("\nSYSCLK9 (CEC CLOCK)\t: %f Mhz\n\n",freq_sysclk[8]);
			printf("-----------------------------------------------------\n");

			/* For FREQ3 */
			value_freq = readPLL(DDRPLL_CTRL, DDRPLL_FREQ3, DDRPLL_DIV3);
			printf("\nFREQ3 : %f Mhz\n\n",value_freq);
			freq_sysclk[7] = value_freq;/* default and only value of divider is 1 */
			printf("\nSYSCLK8 : %f Mhz\n\n",freq_sysclk[7]);
			printf("-----------------------------------------------------\n");

			getdivPLL(DDRPLL_CTRL, DDRPLL_DIV1);
			printf("-----------------------------------------------------\n");

			printf ("\n*******************VIDEOPLL********************\n");
			/* For FREQ1 */
			value_freq = readPLL(VIDEOPLL_CTRL, VIDEOPLL_FREQ1, VIDEOPLL_DIV1);
			printf("\nFREQ1 : %f Mhz\n\n",value_freq);
			prcm_div[10] = (RD_MEM_32(CM_SYSCLK11_CLKSEL) & 0x01) + 1;
			freq_sysclk[10] = value_freq / ((float) prcm_div[10]);
			printf("\nSYSCLK11 : %f Mhz\n\n", freq_sysclk[10]);
			prcm_div_D1 = (RD_MEM_32(CM_VPD1_CLKSEL) & 0x07) + 1;
			value_freq_D1 = value_freq / ((float) prcm_div_D1);
			printf("-----------------------------------------------------\n");
			
			/* For FREQ2 */
			value_freq = readPLL(VIDEOPLL_CTRL, VIDEOPLL_FREQ2, VIDEOPLL_DIV2);
			printf("\nFREQ2 : %f Mhz\n\n",value_freq);
			prcm_div[12] = (RD_MEM_32(CM_SYSCLK13_CLKSEL) & 0x07) + 1;
			freq_sysclk[12] = value_freq / ((float) prcm_div[12]);
			printf("\nSYSCLK13 (HD_VENC_D_CLK): %f Mhz\n\n",freq_sysclk[12]);
			printf("-----------------------------------------------------\n");
			prcm_div_B3 = (RD_MEM_32(CM_VPB3_CLKSEL) & 0x03);
			if (prcm_div_B3 == 0)
				prcm_div_B3 = 1;
			else if (prcm_div_B3 == 1)
				prcm_div_B3 = 2;
			if (prcm_div_B3 == 2)
				prcm_div_B3 = 22;
			
			value_freq_B3 = value_freq / ((float) prcm_div_B3);
			
			/* For FREQ3 */
			value_freq = readPLL(VIDEOPLL_CTRL, VIDEOPLL_FREQ3, VIDEOPLL_DIV3);
			printf("\nFREQ3 : %f Mhz\n\n",value_freq);
			prcm_div[14] = (RD_MEM_32(CM_SYSCLK15_CLKSEL) & 0x07) + 1;
			freq_sysclk[14] = value_freq / ((float) prcm_div[14]);
			printf("\nSYSCLK15 (HD_VENC_A_CLK): %f Mhz\n\n",freq_sysclk[14]);

			prcm_div_C1 = (RD_MEM_32(CM_VPC1_CLKSEL) & 0x03);
			if (prcm_div_C1 == 0)
				prcm_div_C1 = 1;
			else if (prcm_div_C1 == 1)
				prcm_div_C1 = 2;
			if (prcm_div_C1 == 2)
				prcm_div_C1 = 22;
			
			value_freq_C1 = value_freq / ((float) prcm_div_C1);

			printf("-----------------------------------------------------\n");
			
			prcm_div[13] = (RD_MEM_32(CM_SYSCLK14_CLKSEL) & 0x03);
			if (prcm_div[13] == 0)
				freq_sysclk[13] = value_freq_B3;
			else if (prcm_div[13] == 1)
				freq_sysclk[13] = CLKIN;
			else if (prcm_div[13] == 2)
				freq_sysclk[13] = value_freq_C1;
			printf("\nSYSCLK14 : %f Mhz\n\n", freq_sysclk[13]);

			prcm_div[15] = (RD_MEM_32(CM_SYSCLK16_CLKSEL) & 0x01);
			if (prcm_div[15] == 0)
				freq_sysclk[15] = value_freq_D1;
			else if (prcm_div[15] == 1)
				freq_sysclk[15] = value_freq_B3;
				
			printf("\nSYSCLK16 : %f Mhz\n\n", freq_sysclk[15]);
			printf("-----------------------------------------------------\n");

			printf ("*******************AUDIOPLL********************\n");
			/* For FREQ2 */
			value_freq = readPLL(AUDIOPLL_CTRL, AUDIOPLL_FREQ2, AUDIOPLL_DIV2);
			printf("\nFREQ2 : %f Mhz\n\n",value_freq);
			prcm_div[18] = (RD_MEM_32(CM_SYSCLK19_CLKSEL) & 0x07) + 1;
			freq_sysclk[18] = value_freq / ((float) prcm_div[18]);
			printf("\nSYSCLK19 : %f Mhz\n\n",freq_sysclk[18]);
			printf("-----------------------------------------------------\n");

			/* For FREQ3 */
			value_freq = readPLL(AUDIOPLL_CTRL, AUDIOPLL_FREQ3, AUDIOPLL_DIV3);
			prcm_div[19] = (RD_MEM_32(CM_SYSCLK20_CLKSEL) & 0x07) + 1;
			freq_sysclk[19] = value_freq / ((float) prcm_div[19]);
			printf("\nSYSCLK20 : %f Mhz\n\n",freq_sysclk[19]);
			printf("-----------------------------------------------------\n");

			/* For FREQ4 */
			value_freq = readPLL(AUDIOPLL_CTRL, AUDIOPLL_FREQ4, AUDIOPLL_DIV4);
			printf("\nFREQ4 : %f Mhz\n\n",value_freq);
			prcm_div[20] = (RD_MEM_32(CM_SYSCLK21_CLKSEL) & 0x07) + 1;
			freq_sysclk[20] = value_freq / ((float) prcm_div[20]);
			printf("\nSYSCLK21 : %f Mhz\n\n",freq_sysclk[20]);
			printf("-----------------------------------------------------\n");

			/* For FREQ5 */
			value_freq = readPLL(AUDIOPLL_CTRL, AUDIOPLL_FREQ5, AUDIOPLL_DIV5);
			printf("\nFREQ5 : %f Mhz\n\n",value_freq);
			prcm_div[21] = (RD_MEM_32(CM_SYSCLK22_CLKSEL) & 0x07) + 1;
			freq_sysclk[21] = value_freq / ((float) prcm_div[21]);
			printf("\nSYSCLK22 : %f Mhz\n\n",freq_sysclk[21]);
			printf("-----------------------------------------------------\n");

			mcasp0_clk = RD_MEM_32(CM_AUDIOCLK_MCASP0_CLKSEL) & 0x03;
			switch(mcasp0_clk)
			{
			   case 0:
			   	freq_mcasp0 = freq_sysclk[19];
			   case 1:
			   	freq_mcasp0 = freq_sysclk[20];
			   case 2:
			   	freq_mcasp0 = freq_sysclk[21];
			}
			printf("\nMCASP0 CLK = %f\n", freq_mcasp0);

			mcasp1_clk = RD_MEM_32(CM_AUDIOCLK_MCASP1_CLKSEL) & 0x03;
			switch(mcasp1_clk)
			{
			   case 0:
			   	freq_mcasp1 = freq_sysclk[19];
			   case 1:
			   	freq_mcasp1 = freq_sysclk[20];
			   case 2:
			   	freq_mcasp1 = freq_sysclk[21];
			}
			printf("\nMCASP1 CLK = %f\n", freq_mcasp1);
			
			mcasp2_clk = RD_MEM_32(CM_AUDIOCLK_MCASP2_CLKSEL) & 0x03;
			switch(mcasp2_clk)
			{
			   case 0:
			   	freq_mcasp2 = freq_sysclk[19];
			   case 1:
			   	freq_mcasp2 = freq_sysclk[20];
			   case 2:
			   	freq_mcasp2 = freq_sysclk[21];
			}
			printf("\nMCASP2 CLK = %f\n", freq_mcasp2);

			mcbsp_clk = RD_MEM_32(CM_AUDIOCLK_MCBSP_CLKSEL) & 0x03;
			switch(mcbsp_clk)
			{
			   case 0:
			   	freq_mcbsp = freq_sysclk[19];
			   case 1:
			   	freq_mcbsp = freq_sysclk[20];
			   case 2:
			   	freq_mcbsp = freq_sysclk[21];
			}
			printf("\nMCBSP CLK = %f\n", freq_mcbsp);

			break;
			
	      	default:
			printf ("Choose right option\n");
			break;
    }

    close(us_fd);
}