C6678 system, host interrupt pcie intA

serg05

Other Parts Discussed in Thread: SYSBIOS

Hi,

I have some difficulty to use PCIe INTA interrupt. I try to map the sys interrupts to hwi interrupt on two different ways. First set with C Code in main function, second with XGCONF GUI. The two of them don't act. I never observe a interrupt.

I work on custom platform with C6678.

My piece of C code to set up the interrupt.

#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>

volatile unsigned int pcie_inta = 0;

volatile unsigned int event50Done=0;

void event50Fxn(UArg arg)){event50Done = 1;}

void hwi_pcie_inta(UArg arg){pcie_inta =1;}

int main(void){

Ipc_start();

int eventId;

ti_sysbios_family_c64p_Hwi_Params params;

CpIntc_mapSysIntToHostInt(0, 50, 32);

CpIntc_dispatchPlug(50, &event50Fxn, 50, TRUE);

CpIntc_enableHostInt(0, 32);

CpIntc_enableSysInt(0, 50);

eventId = CpIntc_getEventId(32);

Hwi_Params_init(&params);

params.arg = 32;

params.eventId = eventId;

params.enableInt = TRUE;

Hwi_create(4, &hwi_pcie_inta, &params, NULL);

Hwi_enableInterrupt(4);

Hwi_enable();

BIOS_start ();

return 1;}

What have I forgotten? I hope you have further idea.

Regards

over 12 years ago

0 Steven Ji over 12 years ago

TI__Genius 12065 points

Your interrupt setup code seems fine as long as the "event50Fxn" and "hwi_pcie_inta" are defined correctly.

1. May I ask how do you enable the Legacy INTA please?

We need to set bit0 to 1 in LEGACY_A_IRQ_ENABLE_SET (0x21800188) register to enable legacy INTA.

2. May I ask how do you generate the INTA please?

Usually EP device will generate the interrupt and RC device will receive it.

If you are testing the receiving part (PCIe in RC mode), can you confirm if the PCIe link is up and the remote device (EP) generates the interrupt correctly please?

If you are using another C66x device as EP, you can refer to section 2.13.2.1 for the Legacy INT generation in EP mode.

If you are using single C66x device and want to debug the interrupt mechanism, you can enable the Legacy INTA first and set bit0 to 1 in LEGACY_A_IRQ_STATUS_RAW (0x21800180) register to trigger the Legacy INTA to the device itself. It is only used for debugging purpose.

0 serg05 over 12 years ago in reply to Steven Ji

Prodigy 200 points

Hi Steven,

thank you for the answer. I have forgotten to set LEGACY_A_IRQ_ENABLE_SET (0x21800188) register. I get the interrupt now. In which datasheet did you found this setting? I looked up in sprabk8.pdf and sprugs6b.pdf and don't have seen it.

Regards

0 Steven Ji over 12 years ago in reply to serg05

TI__Genius 12065 points

Section 2.13.2.1 in PCIe user guide (sprugs6b) talks about Legacy interrupt generation should be enabled via LEGACY_X_IRQ_ENABLE_SET register (X=A/B/C/D).

I am not sure if you only receive the interrupt in your case. If so, we may need to enable this register for interrupt reception as well. Please let me know. Thanks a lot.

0 serg05 over 12 years ago in reply to Steven Ji

Prodigy 200 points

In my design I only receive the Interrupt INITA via PCIe lines and it was necessary to set the bit 0 in the register LEGACY_A_IRQ_ENABLE_SET.

0 Steven Ji over 12 years ago in reply to serg05

TI__Genius 12065 points

Thanks a lot for confirming this. We will specify this in the PCIe user guide as well.

0 Jeridiah Welti over 9 years ago in reply to Steven Ji

Prodigy 180 points

I am attempting to setup PCIe INTA for a PLX 3380 USB device.

I am setting up the interrupt as follows:

//Map secondary inputs to the Core event
CpIntc_mapSysIntToHostInt(0, 50, 32); // I picked host int 32 for CPINTC #0. CPINTC #1 is for cores 4-7
CpIntc_dispatchPlug(50, &INTA_Event_isr, 50, TRUE); //
CpIntc_enableHostInt(0, 32); // CPINT #0 is for cores 0-3, CPINTC #1 is for cores 4-7
eventId = CpIntc_getEventId(32); // this should return the GEM event 21 (This was a bug fixed in 6.32.04)

Hwi_Params_init(&hwi0Params);
hwi0Params.arg = 32; // required to be the host interrupt #
hwi0Params.eventId = eventId;
hwi0Params.enableInt = TRUE;
hwi0Params.priority = 4;
Hwi_create(6, &hwi_isr, &hwi0Params, NULL); // create ISR to handle this event in Hwi vector 6
Hwi_enableInterrupt(6);
Hwi_enable();

I can manually trigger an event/HWI pair by using this:

((CSL_CPINTC_RegsOvly)CSL_CP_INTC_0_REGS)->STATUS_SET_INDEX_REG = 50;

and everything gets handled correctly, so I have some confidence that my event and HWI are mapped correctly. However if I setup the INTA by setting

LEGACY_A_IRQ_ENABLE_SET and then writing to the LEGACY_A_IRQ_STATUS_RAW, I do not get an event to occur.

What am I missing? Since this is not occuring, I am uncertain if my endpoint is function correctly or not.

I am assuming that Enable_SET is at 0x2180_0188 and _RAW is at 0x2180_0180. When I breakpoint, I can see that these are both set to 0x01, but I do not hit a breakpoint in the event handler as I will when using the CPINTC function above.

0 Jeridiah Welti over 9 years ago in reply to Jeridiah Welti

Prodigy 180 points

As an update using the GEL file from the forum to view interrupts, the below shows that the PCIe Legacy Interrupt A (0) is mapped to host32, as shown above in the code sample, and that the interrupt is enabled, and an interrupt is pending to be serviced. So why does it not trigger the event and ISR on Core 0?

C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: ********************************** PCIE CHANNEL MAP *******************************************
C66xx_0: GEL Output: ***********************************************************************************************

C66xx_0: GEL Output: Protocol Error Interrupt (PCIEXpress_ERR_INT) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: Power Management Interrupt (PCIEXpress_PM_INT) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: Legacy Interrupt Mode 0 (PCIEXpress_Legacy_INT0) ---> INTC0_OUT32
C66xx_0: GEL Output: Legacy Interrupt Mode 1 (PCIEXpress_Legacy_INT1) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: Legacy Interrupt Mode 2 (PCIEXpress_Legacy_INT2) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: Legacy Interrupt Mode 3 (PCIEXpress_Legacy_INT3) ---> INTC0_OUT0 (Interrupts all Cores (broadcast) )
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: ********************************** PCIE EVENTS ENABLE/DISABLE *******************************************
C66xx_0: GEL Output: ***********************************************************************************************

C66xx_0: GEL Output: Protocol Error Interrupt (PCIEXpress_ERR_INT) is **DISABLED**
C66xx_0: GEL Output: Power Management Interrupt (PCIEXpress_PM_INT) is **DISABLED**
C66xx_0: GEL Output: Legacy Interrupt Mode 0 (PCIEXpress_Legacy_INT0) is ##ENABLED##
C66xx_0: GEL Output: Legacy Interrupt Mode 1 (PCIEXpress_Legacy_INT1) is **DISABLED**
C66xx_0: GEL Output: Legacy Interrupt Mode 2 (PCIEXpress_Legacy_INT2) is **DISABLED**
C66xx_0: GEL Output: Legacy Interrupt Mode 3 (PCIEXpress_Legacy_INT3) is **DISABLED**
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: ********************************** PCIE EVENTS RAW STATUS *******************************************
C66xx_0: GEL Output: ***********************************************************************************************

C66xx_0: GEL Output: Protocol Error Interrupt (PCIEXpress_ERR_INT) is ##NOT PENDING##
C66xx_0: GEL Output: Power Management Interrupt (PCIEXpress_PM_INT) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 0 (PCIEXpress_Legacy_INT0) is **PENDING**
C66xx_0: GEL Output: Legacy Interrupt Mode 1 (PCIEXpress_Legacy_INT1) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 2 (PCIEXpress_Legacy_INT2) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 3 (PCIEXpress_Legacy_INT3) is ##NOT PENDING##
C66xx_0: GEL Output: ***********************************************************************************************
C66xx_0: GEL Output: ********************************** PCIE EVENTS ENABLED STATUS *******************************************
C66xx_0: GEL Output: ***********************************************************************************************

C66xx_0: GEL Output: Protocol Error Interrupt (PCIEXpress_ERR_INT) is ##NOT PENDING##
C66xx_0: GEL Output: Power Management Interrupt (PCIEXpress_PM_INT) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 0 (PCIEXpress_Legacy_INT0) is **PENDING**
C66xx_0: GEL Output: Legacy Interrupt Mode 1 (PCIEXpress_Legacy_INT1) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 2 (PCIEXpress_Legacy_INT2) is ##NOT PENDING##
C66xx_0: GEL Output: Legacy Interrupt Mode 3 (PCIEXpress_Legacy_INT3) is ##NOT PENDING##

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C6678 system, host interrupt pcie intA