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The DMA transfer over SYS_NDMAREQ1 not start

Hubert Kempkensteffen
Prodigy 70 points

Hello,
we have the board with the OMAP4460 CPU.
At this board we have connected a DP-RAM on GPMC on the other side sits a microcontroller.
At the moment we exchange the data as follows:
1) in the Linux kernel, a DMA transfer is initiated to GPMC.
2) If the last value has been written into the GPMC from the DMA, the noted opposite the microcontroller and also write data to a different address in the DP-Ram.
3) Then, the microcontroller pulls the pin GPIO61 to low. This then triggers an interrupt in the Linux driver.
4) The Linux drivers are now using DMA data from the GPMC.
5) Finally, the Linux driver sets the GPIO61 input back to HIGH so that the microcontroller in the next cycle can trigger a new interrupt.

This has one disadvantage! We have 2 interrupts, once the hardware interrupt from GPIO61
and the interrupt from the DMA controller.

We have therefore the signal is applied to the set of GPIO61 on SYSNDMAREQ1 and this
Pin match set.
The register of CONTROL_CORE_PAD0_GPMC_NWP_PAD1_GPMC_CLK now looks like this:
CONTROL_CORE_PAD0_GPMC_NWP_PAD1_GPMC_CLK: 0x000B011C
==>
GPMC_NWP_MUXMODE               = 4 == SYS_NDMAREQ1
GPMC_NWP_PULLUDENABLE    = 1
GPMC_NWP_PULLTYPESELEC T =1
GPMC_NWP_INPUTENABLE         =1
The register CCR0 for DMA transport is now on 0x040050C3
DMA4_CCR0[20:19]=0
DMA4_CCR0[4:0]=3
Otherwise, as in the programming software controlled DMA transfer.
See also:
http://e2e.ti.com/support/omap/f/849/t/203703.aspx

But the hardware-driven DMA transfer starts not only the software-controlled,
because we miss something?

Here are all DMA registers:
DMA4_REVISION:     00010900
DMA4_IRQSTATUS_L3: 00000005
DMA4_IRQENABLE_L3: 00000000
DMA4_SYSSTATUS:    00000001
DMA4_CAPS_0:       001C0000
DMA4_CAPS_2:       000001FF
DMA4_CAPS_3:       000000F3
DMA4_CAPS_4:       00007FFE
DMA4_GCR:          00030010
DMA4_CCR0:         040050C3
DMA4_CLNK_CTRL0:   00000000
DMA4_CICR0:        00000922
DMA4_CSR0:         00000000
DMA4_CSDP0:        0000C181
DMA4_CEN0:         00000401
DMA4_CFN0:         00000001
DMA4_CSSA0:        AA3F37FC
DMA4_CDSA0:        010037FC
DMA4_CSEI0:        00000000
DMA4_CSFI0:        00000000
DMA4_CDEI0:        00000000
DMA4_CDFI0:        00000000
DMA4_CSAC0:        A9E87000
DMA4_CDAC0:        00000000
DMA4_CCEN0:        00000000
DMA4_CCFN0:        00000000
DMA4_COLOR0:       00000000
DMA4_CDP0:         00000000
DMA4_CNDP0:        00000000
DMA4_CCCDN0:       00000000

Sincerely Hubert

  • 0
    TI__Expert 8055 points

    Hubert,

    I want to clarify the specific issue that you are facing.  You said:

    "But the hardware-driven DMA transfer starts not only the software-controlled,
    because we miss something?"

    Do you mean that both the hardware and software driven DMA are starting, but you intend for only the software driven DMA to start?

    Regards,
    Gina 

  • 0 in reply to Gina Glaser
    Prodigy 70 points

    Gina,
    sorry for my english.
    I wanted to say     the following    :
    The hardware driven DMA transfer doesnt't start.
    Only the software-controlled DMA-transfer works.

    What are we doing wrong?

    Regards,
    Hubert

  • 0 in reply to Hubert Kempkensteffen
    TI__Expert 8055 points

    Hubert,

    In your other E2E post, you were using the software-triggered (nonsynchronized) DMA transfer, so you followed the sequencing in chapter 16.5.2 of the OMAP4460 TRM.  For hardware-synchronized transfer, you should instead follow the sequencing in chapter 16.5.3 of the OMAP4460 TRM.  Could you please double-check that you are following these steps with the specified order, in order to achieve the final GPMC register values which you posted.

    Thank you,
    Gina 

  • 0 in reply to Gina Glaser
    Prodigy 70 points
    Hello Gina,
    here we go :-). It was not the order was wrong, but I was ordered to take the second sequence 1-11 from Chapter 16.5.3. Section 16.5.2 of the Basic programming is the BIT DMA4_CCRi [5] probably unimportant.

    Thanks Hubert