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MIPI DSI settings for LCD

Haran Ashok
Expert 1175 points

Hi 

We are working on porting MIPI DSI LCD panel (of resolution 1920x1200) on a custom board with OMAP4460. We are using video mode and is configured for one clock pair and four data pairs.

dsi1_dx0
dsi1_dy0 of lane1 ---------------> serial clock lane

dsi1_dx1
dsi1_dy1 of lane 2 ---------------->serial data lane

dsi1_dx2
dsi1_dy2 of lane 3 -----------------> serial data lane

dsi1_dx3
dsi1_dy3 of lane 4 ----------------> serial data lane

dsi1_dx4
dsi1_dy4 of lane5 ------------------> serial data lane

* When the clock lane(lane1) is probed, the observed voltage swig is 100mV.
* When the data lanes (lane2, lane3, lane4, lane5) are probed, the observed voltage swing is 1.2V.

One suspicion for this difference in voltage swing of clock lane and data lanes is buffer drive strength, but no idea whether it is because of buffer drive strength or any other critical factor affecting it. Is there any possibility in MIPI DSI settings to increase the drive strength for the clock lane? Please help me in finding the cause for this difference in voltage swing of clock lane and data lanes.

Thank you

Haran

  • 0
    TI__Intellectual 1035 points

    Hi Haran.

    Those voltages are expected. On MIPI DSI specification, in the DSI Physical Layer defines two operation modes LP(Low power mode) and HS (High Speed mode).

    LP voltage goes around 1.1 to 1.3V
    HS differential voltage goes from 70 to 330 mV

    The actual pixel data is sent across the bus  as high speed serial data, and it is called HS transmission or burst.

    Between transmissions, the differential data signal or Lane goes to the low-power state. So on the data lanes you should see a 1.2V signal followed by a HS burst of data.

    As for the clock it remains in high-speed mode, when you are in video mode. But for command mode (not your case), you should see a non-continuous behavior, as the clock lane should enter LP state between HS data packet transmissions.

    For more details see

    MIPI D-PHY specification

    OMAP4460 TRM Sections

    • 10.3.2.1 DSI PHY
    • 10.3.2.1.1 Data/Clock Configuration
    • 10.3.2.2 DSI Protocol Layer.

    Regards

    Rafael

  • 0
    Prodigy 170 points

    Hi Haran

      I also use MIPI DSI LCD panel ( 960 x 640 ) on a pandaboard es (omap4460). But i can't setup MIPI DSI Lane function work. I can only observe serial clock lane.

    clock lane can be observed on 200mv level. But data lane is always at 1.25V level and can't swing.  Can you help me to setup this part ?

  • 0 in reply to JH Tsou
    TI__Intellectual 1035 points

    The timing between DISPC and DSI is critical. If is not properly configured you won't see anything on the DSI lanes.

    I could help you but please create a new post, and provide the following information, usually available on the panel's datasheet.

    Blankings (hfp, hbp, hsw, vfp,.. etc)

    Bits per pixel.

    Refresh rate.

    PixelClock

    Is it a command mode or video mode panel? How many DSI lanes are used? Which lane is the clock lane, and which are the data lanes?

    Usually there are min, target and max values, please provide them all.

    Also, is there any other chip between OMAP and the panel?

    Regards

    Rafael

  • 0 in reply to Rafael Rodriguez
    Prodigy 10 points

    Rafael,

    Using Pandaboard, I think I am seeing a good DSI video output (as far as I can see from the scope) but it appears that my voltage only goes up to 0.9v instead of 1.2v on LP signals and our receiver chip doesn't appear to comprehend it.  Is there any drive strength settings for the D-PHY?

    Regards,

    Hong