• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 98 subscribers
  • Views 833 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Bit mismatch in Rate dematcher output in BCP PUSCH.

Naveen kumar2
Prodigy 130 points


Hi ,

   I am observing a 4 to 7 bit mismatch  in Rate Dematcher output as well as SSL output for RB Count greater than 12 RBs. The position of bit mismatch is not fixed or without any pattern for differenet number of RBs however position remains same for multiple runs for same RB case.For reference I am taking Matlab Rate Dematcher Output for the same test configuration as given to BCP. We doubted Descrambler so by  disabling descrambler in SSL header we took Demod output and compared with Matlab reference output (by disabling descrambler there also) and found that there is same bit mismatch at same positions as was earlier for 18 RB case.

NOTE: We are doing first stage deinterleaving on Resource Demapped data from Matlab and feeding the same to BCP.

Thanks & Regards

Naveen Kumar

  • 0
    TI__Mastermind 30405 points

    Hi Naveen,

    We have not come across any issues with the Rate Dematcher or SSL output. We don't have a test readily available to run this particular number of RBs so I'll have to check with our design team for that.

    As you mentioned that you see the bit mismatch even in SSL output, it hints towards a potential issue with the input provided to the BCP itself, which is the partially de-interleaved block. Given below is a pseudo-code for stage-1 channel de-interleaving (partial de-interleaving) required before sending the block to the SSL. I would request you to cross check your code against the one given below.

    /* simulate EDMA first stage de-interleaving */

          {

                uint16_t numRowsOver4;

                uint16_t idx1, idx2;

                uint16_t rowIdx, colIdx;

                numRowsOver4 = numUsedSubcars /4; //multiple of 4, number of allocated subcarriers

                for (idx1 = 0; idx1 < numRowsOver4; idx1++)

                {

                      for (idx2 = 0;idx2 < (4 * numPUSCHSymPerSubfrm); idx2++)

                      {

                            rowIdx = (idx1 * 4) + (idx2 &0x3);

                            colIdx = idx2/4;

                            deinterleavedSym [idx1 * 4 * numPUSCHSymPerSubfrm + idx2] = modulatedSym [colIdx * numUsedSubcars + rowIdx ];

                       }

                }                      

          }

    Where deinterleavedSym is BCP input, while modulatedSym is the IDFT outputs from all ofdm symbols in one subframe.

    Regards

    -Nitin

  • 0 in reply to Nitin Sakhuja
    Prodigy 130 points

    Hi Nitin,

    Thanks for reply. We have verified stage 1 Deinterleaving with your given code and ours code also. The results are same in both cases. But stiil we are facing the same bit mismatch issue.

    Thanks & Regards

    Naveen Kumar