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C6678 RSV connections

Team,

On the datasheet it is specified that RSV01 signal should be pulled to 1.8V and RSV08 must be connected to GND,
all other signals are unconnected reserves.
On the evaluation board, RSV08 and RSV01 signals are connected according to the datasheet but
there is a lot of 0R not connected to the ground on the other reserved signals but with internal Pull-down
(RSV02, RSV03, RSV20, RSV21, RSV22).

My customer has doubt about the datasheet accuracy due to those 0R on the EVM, I guess...

Olivier

  • Oliver.

    The Data Manual is correct.  The resistors on the RSV pins other than RSV01 and RSV08 are not installed.  This is shown on the EVM schematic.  The EVM design was completed prior to receiving the first silicon prototypes.  The reserved pins are a combination of test mode control pins and test mode monitor pins.  They needed to be accessible during early chip testing.  Production EVMs have these RSV pins other than RSV01 and RSV08 unconnected as stated in the Data Manual.

    Tom

     

  • Tom,

    What happens if RSV01 and RSV08 are not connected?

     

    We have a board designed two years ago with these two pins not connected (somehow we missed the notes). The board has been running without problem.

     

    Please let me know if this is a critical issue.

     

    Thank you very much.

     

    Chao

  • Chao,

    RSV08 is an analog test input pin used for silicon process characterization.  Allowing it to float is not a problem and will only result in some additional leakage.  Floating RSV01 is a bigger issue.  It is a digital test mode pin that interacts with the DDR3 interface logic.  It needs to be pulled up to DVDD18 to guarantee proper operation.  There is a possibility that the DDR3 interface logic may fail to properly initialize after a reset release if this pin is sampled low.  We recommend that you update your design for future production.

    Tom

     

  • Thank you Tom for quick response.

    Regarding RSV01, the latest datasheet says it  in internal pull down. And our design doesn't have en external pull up resistor. How could our design work?

    We have build many boards (200+) and I never saw DDR3 test failure during bench test (using emulator).

    I'm wondering how could this be possible.

    Regards,

     

    Chao.

  • Chao,

    I did not say it was guaranteed to fail if sampled low.  I said it MAY fail if sampled low.  The DDR3 initialization sequence may be truncated and not be fully JEDEC compliant.  The current board design might not fail.  Then, if a DRAM change is made in the future, it might start failing.

    Tom

     

  • Tom,

    I just measured a few of our boards, the RSV01 pin is at about 1.5V without external pull up resistors.

    We have shipped many boards, do we need to call them back to change?

    FYI: we use I2C boot mode (boot mode 5), in the I2C EPROM, there are 2 boot parameter tables. The boot parameter tables configure PLL, SRIO and set secondary boot mode as SRIO, then we download DSP code through interface.

     

    Thank you again.

    Chao

  • Chao,

    You will have to make the final determination.  If the boards can be easily reworked then I would recommend that this be done.  Alternately, if the boards are functioning robustly then I recommend that you not recall them.  The bottom line is that boards with this pin floating may fail.

    Tom