About Gen2 operation with x2 link on PCIe of DM8168

Hi RY,

According to the DM816x Datasheet, your use case is available:

PCIe® port x2 lanes GEN2 compliant interface, which allows the device to act as a PCIe® root complex or device endpoint;

The device PCIe supports the following features:
 - Supports Gen1 and Gen2 in x1 or x2 mode

There is one bug described in the Silicon Errata which seems related:

Advisory 2.0.44  PCIe Gen2 Mode: PCIESS Corruption of Round-Trip Latency Time and Replay Time Limit Bits (PL_ACKTIMER Register)

Revisions Affected: 2.0, 1.1, 1.0

Details: When the PCIe is operating in Gen2 mode (5-Gbps rate per PCIe link in each direction), writing to either of these bits, round trip latency time limit (RND_TRP_LMT) or the replay time limit (RPLY_LIMT), in the PL_ACKTIMER register causes the value of the bit field that was not being updated to also be modified, corrupting the register contents.

Workaround: Ensure that any updates to either the RND_TRP_LMT or the RPLY_LIMT bits in the PL_ACKTIMER register are made only when the PCIe is operating in Gen1 mode (2.5-Gbps rate per PCIe link in each direction).

Regards,

Pavel