PCIe Inbound Translation is not functioning as I expect

Bill,

You may need to switch the PCIe transaction to supervisor mode in order to access the DSP registers space. 

Basically you can set MST_PRIV bit to 1 in PRIORITY register of PCIe module.

Please take a look at the following thread for details:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/131840.aspx#480784

Additionally, you can use BAR0 to access PCIe application registers space without using inbound translation since BAR0 is dedicated for this purpose. But you still need to let TLP address match the BAR0 value so that PCIe could accept those transactions.

Hi Steven, I'm seeing no change when I change MST_PRIV from 0 to 1.

The original value of PCI_PRIORITY was 0x00000000 and I changed it to 0x00010000.

I've looked at a few additional subsytems, and this is what I've seen so far.

C66x CorePac Revision ID: 0xFFFFFFFF
PCIe PID: 0xFFFFFFFF
PSC PID: 0x44826200
Semaphore PID: 0xFFFFFFFF
EDMA Channel Controller PID: 0x4001AB00
EDMA Transfer Controller 0 PID: 0x40000301

If I swap MST_PRIV to 1, these results stay the same.

Any other ideas?

Bill,

I checked with the design team that there is some limitation for the configuration space access.

1. Semaphore is only allowed to be configuraed by CorePacs and EDMAs due to the privID protection. The only master other than CorePac and EDMA is HyperLink, which allows the extenral host to access Semaphore. But the HyperLink configuration register needs to be appropriately configured, so the remote host can send transactions with the desired privID value (0 to 1 in C6657). 

The other masters (including PCIe) could not access Sempahore configuration space. 

2. CorePac internal registers are private to CorePac itself. They are not accessible by PCIe. If you would like to read the revision ID, you could choose to read the JTAGID register (0x02620018) which is accessible by PCIe master.

3. PCIe application registers are only accessible by using BAR0 register, not other BARn registers. Please try to use BAR0 for this purpose.

Hi Steven,

Thanks for your help with this and my other previous question.

One followup to this, is there a list in the documentation about which regions are not accessible through PCIe? Would this be documented with the preivID protection? (And if so, where might I find that?)

Thanks!

The connections between masters and slaves in the device could be found in the Switch Fabric Connections Matrix (e.g. section 4.2 in C6657 data manual).

You can see that PCIe master port could access most of the slave ports (configuration/memory regions) in the device. 

Semaphore has some limitation as I stated before. We will update the data manual later to specify the limitation for Semaphore. 

Hi Steven,

In one of your above posts you mentioned that CorePac internal resgisters aren't accessible by PCIe. In my application I would like to configure the DSP's DDR registers, PLL registers, EMAC registers, PCI registers, power domain registers and so on using PCIe. Should it be possible?

Could you please specify which of the CorePac resgisters considered internal? Or maybe you can post a link that will exaplin this?

To my understanding every memory-mapped-register isn't considered "internal". Is that correct?

Thanks in advance for your help,

Elad.

Elad,

I think the baseline is still the Switch Fabric Connections Matrix showing the connections between masters and slaves in the device data manual (e.g. section 4.2 in C6657 data manual).

PCIe master port could access MSMC_SES (providing access to DDR EMIF configuration registers), NetCP_CFG (including EMAC registers), PSC (power domain registers), PLL, etc. 

The PCIe configuration registers are only accessible through BAR0 from external PCIe device since PCIe master port is not connected to PCIe slave port (access path to PCIe config space) shown in the connection matrix.

PCIe master port is connected to CorePacN_SDMA port, which gives system masters the access to the CorePac memory space (such as L1/L2 SRAM) but no access to CorePac internal configuration registers, even they are memory mapped registers. Please refer to the note in section "1.2.6 External Memory Controller (EMC)" in CorePac User Guide as follows:

"Note—This port does not provide access to those control registers found within the DSP or the CorePac."

For the other device level registers, you can refer to the matrix for the connection. Most of them should be accessible by PCIe master port with privilege level to be Supervisor (MST_PRIV=1).