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GPMC_FCLK for NAND (micron) in DM8148

Hi,

I am trying to know how the GPMC_FCLK cycles are being calculated for the GPMC NAND interface.

How to increase or decrease the GPMC_FCLK cycles for read,write or any other access in the GPMC_CONFIGi registers.

On what basis do we calculate the number of GPMC_FCLK cycles and how do we calculate the number of GPMC_FCLK cycles? is there any formula or something?

Could someone help me on this?

Thanks

Prakash

  • Prakash,

    You've to first calculate the current frequency which it is set to. Read the NAND datasheet to figure out the expected parameters that you want to tune. This timing info will typically be in nano seconds. Calculate the number clock cycles required for those timing details. Then set the values accordingly. 

    What exactly are you trying to achieve here?

  • Hi Renjith,

    Thanks for your reply.

    Our custom board is taking a long time approximately 70 sec to boot (u-boot and kernel) from NAND. we want to reduce the time to less than 30 secs.

    We have our MPU and GPMC working at their maximum frequency but still the NAND is taking 70 secs to boot the u-boot and kernel. So we thought of changing the GPMC_CONFIGi register values interfaced to NAND, to reduce the time. Could you help us on this regard?

    We are basically looking to reduce the boot time to less than 30secs. Thanks in advance

    Regards

    Prakash

  • Prakash,

    The whole boot time can be brought down to less than 10 seconds. The whole kernel can mount the file-system in less than a second from power on reset. The rest depends on your application, on how much time it takes to boot. 

    Just changing the value in NAND flash config registers may not help much as you have to really optimize the NAND driver in a better way.

  • Renjith,

    We have optimised the NAND driver to our best we could. Is there any other way out for us to reduce the time? 

    Thanks

    Prakash

  • Prakash,

    What is the NAND throughput that you are able to achieve?