Recommended DDR stress testing?

Mike,

Have you tried the memory test command available in u-boot? You can run the command "mtest" to do the testing.

Yes, we use this test while running units in a chamber.

It's not clear to me that this test is exhaustive - For example, does it cover all the timing scenarios that are impacted by the timing configuration registers?  Does it do rapid turn read-the-write or write-then-read cycles, walk randomly opening and closing different rows/banks, etc?  Looking at the code, it doesn't look like a lot of these types of scenarios are considered and the scenarios that are tested are dependent on the CONFIG_SYS_ALT_MEMTEST flag.

The reason why I ask is we may have found a potential configuration issue that was not readily detected by u-Boot's mtest in our chamber test.  So I was soliciting for any other tests techniques we might add to our validation cycle.

-Mike

Mike,

You can't call this as a stress test. It can be a basic sanity test. I don't think there are any memory stress testing tools available readily from TI. Instead you can checkout the standard Linux memtester application available on PC.

Download the code and cross compile it for ARM and run. 

http://pyropus.ca/software/memtester/ 

Hope this helps.

Mike, some other tests that we use are in the GEL files for the different development boards we have.  The GELs can be found here:  http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x

They include a basic read/write test and a test utilizing DMA which will provide a better stress test.  Definitely not a complete stress test that you are looking for, but an alternative.  The GEL code should be easily translated to C if you need to include this in linux kernel or uboot.

Regards,

James

Hi Mike,

You must simulate your layout data with using related IBIS file in corner case (Fast, Slow) not typical for like max. mbps DDR data issues.

And then you can optimize your register settings.

Regards,

FERHAT