Memory access bottleneck with multiple processors

Viswanath L

I am working on a multichannel decoder system on DM8168. What I am oberserving is that the MCPS load of an individual decoder instance is impacted by parallel instances on other processors. To put in clearer terms, say when I have one decoder alone working in the system (on VICP-0), the decoder cycles is X MCPS. When I have two decoders working in parallel (one each on VICP-0 and VICP-1), the cycles of the decoder on VICP-0 becomes 1.3X. When I add two scalers in the system (on VPSS), the decoder MCPS rises to 1.4X. Is this increase attributed to memory conflict between the processors? Any pointers regarding how this can be resolved?

Thanks.

over 12 years ago

0 Pavel Botev over 12 years ago

TI__Guru**** 170625 points

Hello,

Are you on EZSDK or DVR RDK?

Regards,

Pavel

0 Viswanath L over 12 years ago in reply to Pavel Botev

Intellectual 290 points

I am on EZSDK. Any benefit in going to RDK?

0 Pavel Botev over 12 years ago in reply to Viswanath L

TI__Guru**** 170625 points

Hello,

How many decode channels do you need? With EZSDK you can not go beyond 8 channels. EZSDK is not supposed to be used in multichannel cases, due to SNT nature of OMX. For multichannel RDK is recommended.

Best Regards,

Pavel

0 Viswanath L over 12 years ago in reply to Pavel Botev

Intellectual 290 points

I am working with two channels, and the IL client we have does work in SNT mode for multiple channels. My specific concern is regarding the progressive increase in decoder cycles due to interference from other processing cores (please see original post for details).

Thanks.

0 Pavel Botev over 12 years ago in reply to Viswanath L

TI__Guru**** 170625 points

Hello,

I am moving this thread to the Multimedia Codecs forum. I think here you will have the answers.

Regards,

Pavel

0 Vimal Jain over 12 years ago in reply to Pavel Botev

TI__Expert 6535 points

Hi,

How are you measuring the MCPS ? Also what is the resolution ? Ideally 2 channels would not cause the performance issue

Regards

Vimal

0 Viswanath L over 12 years ago in reply to Vimal Jain

Intellectual 290 points

MCPS is measured by profiling the clock ticks from start to end of VDEC process call in VDEC OMX component on M3. The resolution is 1080p60.

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Memory access bottleneck with multiple processors