c6678 EDMA confused Throughput

Si Cheng,

si cheng said:

1 .some tables show that  Aggregate throughput of TCs fired is  larger than Theoretical Max throughput between TC endpoints, it wonder me,for example 

5.6 Scenario 6: EDMA Transfer From Different CorePac L2 to DDR3   table 15. 

When I look at the section you mention, it does not show the measured numbers being larger than the theoretical numbers:

I do not see the problem. Although these numbers are very idealistic, they are still reasonable. Are you looking at the latest release of this Application Note, SPRABK5A dated July 2012?

si cheng said:

2 . it says TC0 and TC1 can work simultaneously， I want know how can I make TC0 and TC1 work  simultaneously,  if I want to make them work simultaneously, what

need I  set ?

You do not need to do anything. If both TC0 and TC1 are loaded with Transfer Requests, then they will be operating simultaneously. This is similar to how running a program on CorePac0 and running another program on CorePac1, both will be running simultaneously.

For the EDMA3 modules, each DMA or QDMA channel will have a CCQueue number assigned to it and that CCQueue number corresponds to a Transfer Controller. If you start two channels that are assigned to different TCs (CCQueues), then those two TCs will be operating simultaneously.

Regards,
RandyP

can you give me the lastest release link of sprabk5a? 

thank you

You need to be able to access all documentation for the device. Please go to the TMS320C6678 Product Folder ( <- red link ) and look for Technical Documents. Under Application Notes you will find this document.

Or you can go to TI.com and search for the document number that you and I have listed above.

Regards,
RandyP