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Disabling L2 Cache

Shahid AC
Expert 2380 points
Other Parts Discussed in Thread: SYSBIOS

Hello,

Could some tell me whether Cache_inv API will invalidate L2 cache contents? If not,  are there any other sysbios APIs which I can call from my application to invalidate all L2 and L1 cache contents ?

I am asking this because the asm function called by Cache_inv API looks to be invalidating L1 cache only. The asm function getting called is "ti_sysbios_family_arm_a8_Cache_invL1p__I". 

I am working on AM335x paltform with  sysbios version 6.33.5.46 and xdctools 3.23.3.53

Thanks in advance,

Shahid

  • 0
    TI__Mastermind 30830 points

    Shahid,

    To my understanding, the ARM cache architecture does not allow independent invalidation of the L2 cache.

    The Cache_Type argument to Cache_inv() will determine whether program or data or both caches will be invalidated.

    The instruction used for invalidating the instruction cache is:

            mcr     p15, #0, r0, c7, c5, #1

    which "Invalidates instruction cache line by MVA to PoC".

    The instruction used for invalidating the data cache is:

            mcr     p15, #0, r0, c7, c6, #1 ;

    which "Invalidates Data or Unified cache line by MVA to PoC".

    Here is ARM's definition of POC:

    "Point of coherency

    The time when the imposition of any more cache becomes transparent for instruction, data, and translation table walk accesses to that address by any processor in the system."

    In this context, my understanding of PoC (Point of Coherency) is that all caches are invalidated (ie if L2 is enabled, it will be invalidated as well).

    Alan