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About the DDR_Init function in the TI example code KeyStone_SRIO

David Yang1
Intellectual 435 points


Hi,TI guys:

I am working on the KeyStone_SRIO example in both 6670EVM and 6678EVM. Digital loopback worked just OK on both of the EVM. But when I check the DDR_Init function for Shannon and for Nyquist, I got confused that there are such a big difference between them. But both EVM has the same four samsung DDR, where did those difference come from?

The difference, I quote:

In 6678, the row size is configured as 13bit

(DDR_ROW_SIZE_13_BIT<<CSL_EMIF4F_SDRAM_CONFIG_REG_ROWSIZE_SHIFT)

In 6670, the row size is configured as 14bit

DR_ROW_SIZE_14_BIT<<CSL_EMIF4F_SDRAM_CONFIG_REG_ROWSIZE_SHIFT)

also，the leveling init code is quite different:

in 6670;

//initial vale for leveling 
/*WRLVL_INIT_RATIO*/ 
boot_cfg_regs->DDR3_CONFIG_REG[2] = 0x0F; 
boot_cfg_regs->DDR3_CONFIG_REG[3] = 0x0F; 
boot_cfg_regs->DDR3_CONFIG_REG[4] = 0x20; 
boot_cfg_regs->DDR3_CONFIG_REG[5] = 0x24; 
boot_cfg_regs->DDR3_CONFIG_REG[6] = 0x33; 
boot_cfg_regs->DDR3_CONFIG_REG[7] = 0x38; 
boot_cfg_regs->DDR3_CONFIG_REG[8] = 0x21; 
boot_cfg_regs->DDR3_CONFIG_REG[9] = 0x29; 
boot_cfg_regs->DDR3_CONFIG_REG[10] = 0x0 ; 

/*GTLVL_INIT_RATIO*/ 
boot_cfg_regs->DDR3_CONFIG_REG[14] = 0x7B; 
boot_cfg_regs->DDR3_CONFIG_REG[15] = 0x7B; 
boot_cfg_regs->DDR3_CONFIG_REG[16] = 0x8D; 
boot_cfg_regs->DDR3_CONFIG_REG[17] = 0x89; 
boot_cfg_regs->DDR3_CONFIG_REG[18] = 0xC0; 
boot_cfg_regs->DDR3_CONFIG_REG[19] = 0xBC; 
boot_cfg_regs->DDR3_CONFIG_REG[20] = 0xC3; 
boot_cfg_regs->DDR3_CONFIG_REG[21] = 0xBB; 
boot_cfg_regs->DDR3_CONFIG_REG[22] = 0x0 ;

and in 6678

/initial vale for leveling
/*GTLVL_INIT_RATIO*/
boot_cfg_regs->DDR3_CONFIG_REG[14] = 0xA1;
boot_cfg_regs->DDR3_CONFIG_REG[15] = 0x9E;
boot_cfg_regs->DDR3_CONFIG_REG[16] = 0xA7;
boot_cfg_regs->DDR3_CONFIG_REG[17] = 0xA9;
boot_cfg_regs->DDR3_CONFIG_REG[18] = 0xCA;
boot_cfg_regs->DDR3_CONFIG_REG[19] = 0xBE;
boot_cfg_regs->DDR3_CONFIG_REG[20] = 0xDD;
boot_cfg_regs->DDR3_CONFIG_REG[21] = 0xDD;
boot_cfg_regs->DDR3_CONFIG_REG[22] = 0xBA;

/*WRLVL_INIT_RATIO*/
boot_cfg_regs->DDR3_CONFIG_REG[2] = 0x20;
boot_cfg_regs->DDR3_CONFIG_REG[3] = 0x24;
boot_cfg_regs->DDR3_CONFIG_REG[4] = 0x3A;
boot_cfg_regs->DDR3_CONFIG_REG[5] = 0x38;
boot_cfg_regs->DDR3_CONFIG_REG[6] = 0x51;
boot_cfg_regs->DDR3_CONFIG_REG[7] = 0x5E;
boot_cfg_regs->DDR3_CONFIG_REG[8] = 0x5E;
boot_cfg_regs->DDR3_CONFIG_REG[9] = 0x5E;
boot_cfg_regs->DDR3_CONFIG_REG[10] = 0x44;

and in 6670 there are some extra code 

/*the PHY_RESET is pulsed (0 -> 1 -> 0) to latch these 
leveling configuration values into the PHY logic.*/
DDR_Regs->DDR_PHY_CTRL_1 &= ~(0x00008000);
DDR_Regs->DDR_PHY_CTRL_1 |= (0x00008000);
DDR_Regs->DDR_PHY_CTRL_1 &= ~(0x00008000);

there is leveling in c6678, too. Why is the difference?

The reason why  looked in to the DDR_init code is that I tried the  KeyStone_SRIO example on a board(not the EVM) , with 2 6670DSP ,each of them has 2DDRs(same samsung DDR).The DDR_init always failed , with the values of STATUS_REG_RDLVLGATE, TATUS_REG_RDLVLT, and STATUS_REG_WRLVL in DDR_Regs->STATUS  all 1,which indicated time out error.

My question is where does the big difference of DDR_Init of 6670&6678 come from? And if I had a 6670 DSP with 2, not 4, same DDR, how shall alter the code, Given that I already now the DDR clock requency on board.

Thanks ~

  • 0
    TI__Guru* 84110 points

    David,

    I am sorry no one has addressed your questions yet, but I expect it is a difficult task to go back and re-analyze what has been done to explain why a helpful example works.

    You have said that both examples work. Have you performed DDR tests on both EVMs and confirmed that they are indeed configured correctly? Or is there a problem with either of the EVM doing a DDR test? I cannot rule out that one of the row size settings is incorrect, but I am a user like yourself and would not be able to tell you why there are these differences without going through the DDR initialization process like you need to do for your own board.

    The Hardware Design Guide and DDR Requirements and the new DDR3 Initialization Application Notes are the documents you need to use to help you determine the correct values to use for your new board. You may want to copy the code from the EVM examples, but you will want to use the values that you calculate based on your study using these Application Notes.

    Do not expect the exact same code+data that works for the EVMs to work for your custom board. There are characteristics of your board that must be used to determine some of the values. The Application Notes above will help you understand the procedures to follow, from board design to board bring-up.

    If your board has C6670 devices, then you may use the example from the EVM as a starting point, but do not expect it to work exactly as it comes with the EVM.

    David Yang1 said:
    My question is where does the big difference of DDR_Init of 6670&6678 come from? And if I had a 6670 DSP with 2, not 4, same DDR, how shall alter the code, Given that I already now the DDR clock requency on board.

    Instead of trying to explain why two different boards' init files work for those different boards, assuming that they do work correctly for both board, it is best to try to get your real goal accomplished which is to get your own board working. Going through the three Application Notes first will help you achieve that, then please come back here with any questions you have about the procedure that you followed there. Following these three Application Notes should lead you to your successful board bring-up.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 435 points

    RandyP,

    Thank you so much for your answers, and your patience as well. I tried both init examples on both EVMs, and their ddrs both workrd correctly. However, when I deleted the DDR init code from the example for my own board, and used the gel file for 6670evm, which included the ddr3 init code, my ddr magically worked correctly. The init code in gel is not as same as those in the KeyStone_SRIO examples. I downloaded the file you recommanded and I am trying to find out why . Anyway, you are of great help, thanks again. And I have any questions, I will come back.

    Regards,

    David