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the input clock of C6678

cong wang
Prodigy 50 points

When I  use 100MHz as the reference input clock(LVDS), the DSP can work well. Why  the DSP can't work using 66.67MHz or 156.25Mz (LVDS) as the reference input clock? And I have modified the BOOT MODE[12:10], is there somewhere to modify?

Thanks

  • 0
    TI__Mastermind 30825 points

    What Bootmode are you using?  Have you verified it's been latched (connecting with CCS and checking the BOOTMODE field of the DEVSTAT register?)  Have you checked what frequency you're seeing at the SYSCLKOUT?  It would be at CPU/6 rate so you can multiply it by 6 and verify if you've got the right clocking.

    Best Regards,
    Chad

  • 0 in reply to Chad Courtney
    Prodigy 50 points

    Thanks for your answer! When I use the 66.67MHz or 156.25MHz as input clock, JATG can't connect to the DSP.This is the question puzzling me.

    Best Regards

  • 0 in reply to cong wang
    TI__Mastermind 30825 points

    Did you check the SYSCLKOUT?  What did you get?  Did you probe the BOOTMODE Pins during PORz to see what should have been latched?  What are these values?

    My guess is the bootmode being driving in is incorrect or something along those lines, but right now there's very little to go on.  Please not that there are no issues w/ using the SYSCLK across the documented supported SYSCLK input range, and this has been fully tested.  Based on this, I can only assume something wasn't setup correctly for booting the device.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Prodigy 50 points

    Thank you! I have solved the problem