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SRIO doorbell Interrupt doesn't raise Event handler

Sajin SA
Prodigy 20 points

        I am facing a problem with the event handler to SRIO doorbell interrupt in C6455 DSP. The doorbell interrupts are routed to Rapid IO Interrupt 4 (EVENT ID 22, INTDST4)(through DOORBELL0_ICRR registers) which is mapped to CPUINT4. The event handler  is attached  to CPUINT4 / EVENT ID 22 using CSL_intcPlugEventHandler(). But the event handler is raised  ONLY for the first doorbell packet received after power on.

     The doorbell status register DOORBELL_ICSR0 is set properly on receiving each doorbell packet. But the interrupt is NOT reflected in corresponding  Event Flag register (EVTFLAG0) and Interrupt Flag register (IFR). (CPUINT4 enabled in IER register. GIE enabled in CSR register. The corresponding bits in DOORBELL0_ICSR and EVENT_FLAG0  registers are cleared after the first interrupt.)

Please  suggest any ideas to solve this issue?  Thank you in advance.

  • 0
    TI__Guru* 84110 points

    Sajin,

    The fact that you get the first doorbell to raise the event handler means that you have the correct interrupt routing implemented. Good work on that part.

    Have you implemented everything in the SRIO User's Guide Section 4.8 Interrupt Handling?

    The implication from your situation is that you are not properly clearing all of the status of the existing interrupt so that the C64x+ MegaModule does not see a transition on the interrupt line internally.

    You may debug this by tracing back the signals going to the IFR register: INTC and SRIO modules, to figure out the status of the doorbell and interrupt signals.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 20 points

    RandyP,

              Thank you for the quick response . The problem is now solved.

              It was the INTDSTn_RATE_CNTL register, which was not reloaded after the first interrupt. What I missed is that “If interrupt pacing is not desired for a particular interrupt destination, CPU must still write 0x00 into the INTDSTn_RATE_CNTL register after  learing the corresponding ICSR bits to acknowledge the physical interrupt.” – Section 4.7 Interrupt Pacing

    Regards,

    Sajin S A

  • 0 in reply to Sajin SA
    TI__Guru* 84110 points

    Sajin,

    Most importantly, we are glad your problem is solved. It is also important that you replied back with your solution. That will save many users the time you spent debugging this, and that is why I marked your post as a Verified Answer. That will help future readers know to pay special attention to that post.

    We look forward to more interaction with you as you build your project to success.

    Regards,
    RandyP