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Hi all
I have a query regarding AIF2.
I am working on EVM 6678.
Is AIf2 loopback mode supported in TDD LTE configuration if i have to test through serdes loopback ?
BR
Rahul
Hi,
AIF2 support TDD LTE mode for both Egress and Ingress and that means you can test UL or DL scenario by SERDES loopback. in that case, your TDD setup for PE and PD should be identical.
Albert
Hi Albert
Thanks for the reply.
So it means AIF2 supports the scenario if PD module is catching packets for downlink (loopback mode).
Further, what i understand is PD and PE works independently.Is it right?
While testing this loop back mode i am sporadically getting a PE error when checking EE Link Raw Status B Register (PE_symbol_error) Why is PE giving this error ?
Hi , see my answer below.
So it means AIF2 supports the scenario if PD module is catching packets for downlink (loopback mode). [AB] yes. or you can use uplink data for Egress and you can catch uplink data on Ingress. it depends on your configuration.
Further, what i understand is PD and PE works independently.Is it right? [AB] yes. but configuration looks similar when we use loopback mode.
While testing this loop back mode i am sporadically getting a PE error when checking EE Link Raw Status B Register (PE_symbol_error) Why is PE giving this error [AB] pe symbol error occurs when the symbol number in the PS field of mono descriptor is not matched with the PE symbol processing order. you need to check your application how create symbol number field for each descriptor.
Regards,
Albert
Hi
The question is regarding LTE TDD configuration,The AIF2 UG says
"This 144 bits correspond to each symbol and these bit maps work per bit to support several radio standards. For LTE, there are 120 or 140 symbols in one frame for
UL or DL; the user can only set each bit to one or zero for their purpose".
i use TDD configuration0 so there will be 120 symbols in a frame, then how to map 144 AIF2 bits to 120 symbols,is it direct mapping?
Can you please elaborate more on this.
Regards
Rudresh
Yes, it is direct mapping. pd_dmachan_b register tdd_en field has 16 bit and the bit 16 is matched with symbol 0.
bit 17 for symbol1, bit 18 for symbol2 ......... pd_dmachan_f register bit 7 symbol 119
Regards,
Albert
Dear Albert,
Thank you.
1.why first 15 bits(bit0 to 14) of pd_dmachan_b register tdd_en field are not used and on what basis the symbol0 is mapped on to bit 16 of pd_dmachan_b register,(why can't it start from bit1).
Baisclly,i would like to know the mapping of 144bits for different TDD (symbol) frame configurtion.
2.Does availability of 144 bits implies that AIF2 can support maximum of 144 symbols per radio frame?
3. Can you provide example configurtion/code for LTE TDD.
Regards
Rudresh
Albert Bae said:
Albert Bae said:
Hi,
for some reasons, my previous comment was removed. here, I attached LTE TDD example again. I don't have CPRI example but you can easily apply it with the same way.
we support max 140 symbols for LTE, so you don't need to set the final four bits.
/****************************************************************************\ * Copyright (C) 2009 Texas Instruments Incorporated. * * All Rights Reserved * * * * GENERAL DISCLAIMER * * ------------------------------------------------------------------------ * * All software and related documentation is provided "AS IS" and without * * warranty or support of any kind and Texas Instruments expressly disclaims* * all other warranties, express or implied, including, but not limited to, * * the implied warranties of merchantability and fitness for a particular * * purpose. Under no circumstances shall Texas Instruments be liable for * * any incidental, special or consequential damages that result from the * * use or inability to use the software or related documentation, even if * * Texas Instruments has been advised of the liability. * **************************************************************************** * * * Written by : * * Albert Bae * * Texas Instruments * * 15 July, 2010 * *this example shows how LTE 20 MHz TDD mode is working. it transfers four DL symbols *and skip three UL symbol place and send 7 symbols again. ***************************************************************************/ #include <stdio.h> #include <stdlib.h> #include <string.h> #include <c6x.h> #include <ti/csl/src/intc/csl_intc.h> #include <ti/csl/csl_cacheAux.h> #include "Aif2_config.h" #include "psc_util.h" /* Define queues for common FDQs */ #define MONO_TX_COMPLETE_Q 2000 #define MONO_RX_FDQ 2001 /* These are for the AIF test */ #define MONO_RX_Q 900 #define MONO_TX_Q 512 //Users should use 16 bytes aligned data for Aif2 and pkt dma test #pragma DATA_SECTION(mono_region,".intData_sect")//use MSMC memory for this test #pragma DATA_ALIGN (mono_region, 16) Uint8 mono_region[32 * 8848];//payload size is 8.8K bytes for Normal cyclic prefix 20 MHz LTE Uint32 tmp[14], symindex = 0; Uint32 EE_linkB_Raw[160]; Uint32 EgressEOP[160]; Uint32 IngressEOP[160]; /* Intc variable declarartion */ CSL_IntcObj intcObj; CSL_IntcHandle hIntc; CSL_IntcEventHandlerRecord EventHandler[8]; CSL_IntcGlobalEnableState state; /* Global structures and variables */ CSL_Aif2Obj Aif2Obj;// Aif2 CSL object CSL_Aif2Handle hAif2;// Aif2 handle Bool ctrlArg; // Ctrl Argument; CSL_Aif2Context Aif2Context;//Aif2 context CSL_Aif2Param aif2Param;//AIF2 module specific parameters CSL_Status status; // CSL status CSL_Aif2Setup aif2Setup;//Aif2 HW setup CSL_Aif2LinkSetup linkSetup;// Setup for links CSL_Aif2GlobalSetup globalSetup;// global config for AIF2 CSL_Aif2CommonSetup commonSetup; // Setup for common params CSL_Aif2SdCommonSetup SdCommonSetup;//SERDES common setup CSL_Aif2PdCommonSetup PdCommonSetup;//PD common setup CSL_Aif2PeCommonSetup PeCommonSetup;//PE common setup CSL_Aif2IngrDbSetup IngrDbSetup;// Ingress data buffer setup CSL_Aif2EgrDbSetup EgrDbSetup;// Egress data buffer setup CSL_Aif2AdCommonSetup AdCommonSetup;// Aif2 DMA common setup CSL_Aif2AtCommonSetup AtCommonSetup; // Aif2 Timer common setup CSL_Aif2AtEventSetup AtEventSetup; // Aif2 Timer external and internal event setup CSL_Aif2AtCountObj PhyTimerTc;// AT Phy Terminal Count setup CSL_Aif2AtCountObj RadTimerTc;// AT Rad Terminal Count setup CSL_Aif2AtCountObj PhyTimerInit;// AT Phy Init value setup CSL_Aif2AtCountObj RadTimerInit;// AT Rad Init value setup CSL_Aif2CommonLinkSetup ComLinkSetup; // Aif2 link common setup CSL_Aif2SdLinkSetup SdLinkSetup; //SERDES link setup CSL_Aif2RmLinkSetup RmLinkSetup; //RM link setup CSL_Aif2TmLinkSetup TmLinkSetup; //TM link setup CSL_Aif2PdLinkSetup PdLinkSetup; //PD link setup CSL_Aif2PeLinkSetup PeLinkSetup; //PE link setup CSL_Aif2RtLinkSetup RtLinkSetup; //RT link setup CSL_Aif2AtLinkSetup AtLinkSetup; // Aif2 timer link setup (Pi, Delta, PE signal) volatile unsigned int int4_result; interrupt void int4_isr(){ if((int4_result >= 140) && (int4_result <= 143)){// first DL four symbols push_queue(MONO_TX_Q, 1, 0, tmp[symindex]); symindex++; } else if(int4_result == 146) symindex = 7; else if((int4_result >= 147) && (int4_result <= 153)){// second DL seven symbols push_queue(MONO_TX_Q, 1, 0, tmp[symindex]); symindex++; } EE_linkB_Raw[int4_result] = hAif2->regs->EE_LK[0].EE_LK_IRS_B; EgressEOP[int4_result] = hAif2->regs->DB_EDB_EOP_CNT; IngressEOP[int4_result] = hAif2->regs->AD_ISCH_EOP_CNT; if(int4_result == 140) hAif2->regs->EE_LK[0].EE_LK_IRS_CLR_B = 0xFFFFFFFF; int4_result++; } void Intc_config(void) { CSL_IntcParam vectId; CSL_IntcContext context; //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!// //! GEM0 Intc Configuration !// //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!// /* Setup the global Interrupt */ context.numEvtEntries = 8; context.eventhandlerRecord = EventHandler; CSL_intcInit(&context); /* Enable NMIs */ CSL_intcGlobalNmiEnable(); /* Enable Global Interrupts */ CSL_intcGlobalEnable(&state); /* VectorID for the Global Edma Event */ vectId = CSL_INTC_VECTID_4; /* Opening a handle for the Fsync->EDMA Interrupt Event */ hIntc = CSL_intcOpen(&intcObj, AIF2_EVENT7_INTSEL_MAP, // Event 7 &vectId, NULL); //Hook the ISRs CSL_intcHookIsr(vectId, &int4_isr); // Clear the Interrupt CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTCLEAR, NULL); //Enable the Event & the interrupt CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTENABLE, NULL); } void MNavigator_config(void) { Uint32 flow_a; Uint32 flow_d; Uint16 idx; MNAV_MonolithicPacketDescriptor *mono_pkt; /* Setup Memory Region 0 for 32 8848B Monolithic descriptors. Our * Mono descriptors will be 12 bytes plus 4 bytes protocol specific field, plus * 8832(8768) bytes of payload(symbol). so the total size is 8848 and it is dividable by 16 * total number of descriptors is 32 */ set_memory_region(0, (Uint32) mono_region, 0, 0x02280000); /***************************************************************** * Configure Linking RAM 0 for the descriptor regions. */ set_link_ram(0, QM_LRAM_REGION, 0x3fff); //internal link ram /* Initialize descriptor regions to zero */ memset(mono_region, 0, 32 * 8848); /* Push 16 Monolithic packets into Tx Completion Queue */ for (idx = 0; idx < 16; idx ++) { mono_pkt = (MNAV_MonolithicPacketDescriptor *)(mono_region + (idx * 8848)); mono_pkt->type_id = MNAV_DESC_TYPE_MONO; mono_pkt->data_offset = 16; mono_pkt->pkt_return_qmgr = 0; mono_pkt->pkt_return_qnum = MONO_TX_COMPLETE_Q; push_queue(MONO_TX_COMPLETE_Q, 1, 0, (Uint32)(mono_pkt)); } /* Push 16 Monolithic descriptors to Rx FDQ */ for (idx = 16; idx < 32; idx ++) { mono_pkt = (MNAV_MonolithicPacketDescriptor *)(mono_region + (idx * 8848)); mono_pkt->type_id = MNAV_DESC_TYPE_MONO; mono_pkt->data_offset = 16; push_queue(MONO_RX_FDQ, 1, 0, (Uint32)(mono_pkt)); } /***************************************************************** * Configure Rx channel flows */ /* Note that when LOOPBACK_MODE is enabled, the PKTDMA will force * force the flow ID value in the Tx Streaming I/F to be equal to * the channel number. (normally, the Tx flow ID is set to 0xff). * This is a simulator special testing feature. */ //Create flow configuration 0 for the Monolithic packets flow_a = 0x28100000 | MONO_RX_Q; flow_d = MONO_RX_FDQ << 16; config_rx_flow(AIF_PKTDMA_RX_FLOW_REGION, 0, flow_a, 0, 0, flow_d, 0, 0, 0, 0); /***************************************************************** * Enable Tx and Rx channels. */ enable_disable_loopback(0);//disable PktDMA loopback for normal data transfer config_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, 0, 0x01000000); //set AIF_MONO_MODE to 1 and set PS filter to zero enable_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, 0, 0x80000000); enable_rx_chan(AIF_PKTDMA_RX_CHAN_REGION, 0, 0x80000000); } void Aif2_MNAV_Obsai_config(void) { int i; /************ Initialize Aif2 structures to avoid unwanted configuration ************************************************/ memset(&globalSetup, 0, sizeof(globalSetup)); memset(&linkSetup, 0, sizeof(linkSetup)); memset(&commonSetup, 0, sizeof(commonSetup)); memset(&SdCommonSetup, 0, sizeof(SdCommonSetup)); memset(&PdCommonSetup, 0, sizeof(PdCommonSetup)); memset(&PeCommonSetup, 0, sizeof(PeCommonSetup)); memset(&IngrDbSetup, 0, sizeof(IngrDbSetup)); memset(&EgrDbSetup, 0, sizeof(EgrDbSetup)); memset(&AdCommonSetup, 0, sizeof(AdCommonSetup)); memset(&AtCommonSetup, 0, sizeof(AtCommonSetup)); memset(&AtEventSetup, 0, sizeof(AtEventSetup)); memset(&PhyTimerInit, 0, sizeof(PhyTimerInit)); memset(&RadTimerInit, 0, sizeof(RadTimerInit)); memset(&PhyTimerTc, 0, sizeof(PhyTimerTc)); memset(&RadTimerTc, 0, sizeof(RadTimerTc)); memset(&ComLinkSetup, 0, sizeof(ComLinkSetup)); memset(&SdLinkSetup, 0, sizeof(SdLinkSetup)); memset(&RmLinkSetup, 0, sizeof(RmLinkSetup)); memset(&TmLinkSetup, 0, sizeof(TmLinkSetup)); memset(&PdLinkSetup, 0, sizeof(PdLinkSetup)); memset(&PeLinkSetup, 0, sizeof(PeLinkSetup)); memset(&RtLinkSetup, 0, sizeof(RtLinkSetup)); memset(&AtLinkSetup, 0, sizeof(AtLinkSetup)); // Initialize CSL library, this step is required CSL_aif2Init(&Aif2Context); // Open Aif2 and get handle hAif2 = CSL_aif2Open(&Aif2Obj, CSL_AIF, &aif2Param, &status); if ((hAif2 == NULL) || (status != CSL_SOK)) { printf ("\nError opening CSL_AIF2"); exit(1); } /************** populating AIF2 major setup structures ***************************************************/ aif2Setup.globalSetup = &globalSetup; aif2Setup.commonSetup = &commonSetup; aif2Setup.linkSetup[CSL_AIF2_LINK_0] = &linkSetup;//assign only one link setup for link 0 // populate global config fields globalSetup.ActiveLink[CSL_AIF2_LINK_0] = TRUE;//Activate link 0 for this test globalSetup.frameMode = CSL_AIF2_FRAME_MODE_NORMAL; //populate common config fields commonSetup.pSdCommonSetup = &SdCommonSetup; commonSetup.pPdCommonSetup = &PdCommonSetup; commonSetup.pPeCommonSetup = &PeCommonSetup; commonSetup.pIngrDbSetup = &IngrDbSetup; commonSetup.pEgrDbSetup = &EgrDbSetup; commonSetup.pAdCommonSetup = &AdCommonSetup; commonSetup.pAtCommonSetup = &AtCommonSetup; commonSetup.pAtEventSetup = &AtEventSetup; /****Link Setup (Do this setup repeatedly with different link setup structure if user wants to use multiple links) ***/ //populate link config fields for link 0 linkSetup.linkIndex = CSL_AIF2_LINK_0; linkSetup.pComLinkSetup = &ComLinkSetup; linkSetup.pSdLinkSetup = &SdLinkSetup; linkSetup.pRmLinkSetup = &RmLinkSetup; linkSetup.pTmLinkSetup = &TmLinkSetup; linkSetup.pPdLinkSetup = &PdLinkSetup; linkSetup.pPeLinkSetup = &PeLinkSetup; linkSetup.pRtLinkSetup = &RtLinkSetup; linkSetup.pAtLinkSetup = &AtLinkSetup; //Link Common setup ComLinkSetup.linkProtocol = CSL_AIF2_LINK_PROTOCOL_OBSAI; ComLinkSetup.linkRate = CSL_AIF2_LINK_RATE_4x; ComLinkSetup.IngrDataWidth = CSL_AIF2_DATA_WIDTH_16_BIT; ComLinkSetup.EgrDataWidth = CSL_AIF2_DATA_WIDTH_16_BIT; //SD link setup SdLinkSetup.rxAlign = CSL_AIF2_SD_RX_COMMA_ALIGNMENT_ENABLE; SdLinkSetup.rxLos = CSL_AIF2_SD_RX_LOS_ENABLE; SdLinkSetup.rxCdrAlgorithm = CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_1; SdLinkSetup.rxInvertPolarity = CSL_AIF2_SD_RX_NORMAL_POLARITY; SdLinkSetup.rxTermination = CSL_AIF2_SD_RX_TERM_COMMON_POINT_0_7 ;//for AC coupled application SdLinkSetup.rxEqualizerConfig = CSL_AIF2_SD_RX_EQ_ADAPTIVE;//Equalizer On SdLinkSetup.bRxEqHold = FALSE;//fixed value SdLinkSetup.bRxOffsetComp = TRUE;//fixed value SdLinkSetup.bEnableTxSyncMater = TRUE; //fixed value SdLinkSetup.txInvertPolarity = CSL_AIF2_SD_TX_PAIR_NORMAL_POLARITY; SdLinkSetup.txOutputSwing = CSL_AIF2_SD_TX_OUTPUT_SWING_14; SdLinkSetup.txPrecursorTapWeight = CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_2;// -5% SdLinkSetup.txPostcursorTapWeight = CSL_AIF2_SD_TX_POST_TAP_WEIGHT_24;// -20% SdLinkSetup.bTxFirFilterUpdate = TRUE;//FIR filter update on //TM link setup TmLinkSetup.bEnableTmLink = TRUE; TmLinkSetup.bEnableRmLos = FALSE; TmLinkSetup.SeedValue = 0x1; TmLinkSetup.bEnableScrambler = FALSE; //RM link setup RmLinkSetup.bEnableRmLink = TRUE; RmLinkSetup.RmFifoThold = CSL_AIF2_RM_FIFO_THOLD_IMMEDIATELY; RmLinkSetup.RmErrorSuppress = CSL_AIF2_RM_ERROR_ALLOW; RmLinkSetup.bEnableSdAutoAlign = FALSE; RmLinkSetup.bEnableScrambler = FALSE; RmLinkSetup.bEnableLcvUnsync = FALSE; RmLinkSetup.bEnableLcvControl = FALSE; RmLinkSetup.bEnableWatchDog = FALSE; RmLinkSetup.WatchDogWrap = 0xFF;//set watch dog wrap value RmLinkSetup.bEnableClockQuality = FALSE; RmLinkSetup.ClockMonitorWrap = 0;//disabled RmLinkSetup.losDetThreshold = RM_LOS_DET_THOLD; RmLinkSetup.SyncThreshold = RM_SYNC_THOLD; RmLinkSetup.FrameSyncThreshold = RM_SYNC_THOLD; RmLinkSetup.UnsyncThreshold = RM_UNSYNC_THOLD; RmLinkSetup.FrameUnsyncThreshold = RM_UNSYNC_THOLD; //RT link setup RtLinkSetup.CiSelect = CSL_AIF2_LINK_0; RtLinkSetup.bEnableEmptyMsg = TRUE; RtLinkSetup.RtConfig = CSL_AIF2_RT_MODE_TRANSMIT;// takes PE input only //PD link setup PdLinkSetup.bEnablePdLink = TRUE; PdLinkSetup.Crc8Poly = CRC8_POLY; PdLinkSetup.Crc8Seed = CRC8_SEED; PdLinkSetup.PdTypeLut[OBSAI_TYPE_LTE].ObsaiTsFormat = CSL_AIF2_TSTAMP_FORMAT_NORM_TS; PdLinkSetup.PdTypeLut[OBSAI_TYPE_LTE].PdCrcType = CSL_AIF2_CRC_16BIT; PdLinkSetup.PdTypeLut[OBSAI_TYPE_LTE].bEnableCrc = FALSE; PdLinkSetup.PdTypeLut[OBSAI_TYPE_LTE].PdObsaiMode = CSL_AIF2_PD_DATA_AXC; PdLinkSetup.PdTypeLut[OBSAI_TYPE_LTE].bEnableEnetStrip = FALSE; PdLinkSetup.PdTypeLut[OBSAI_TYPE_LTE].bEnableCrcHeader = FALSE; //PE link setup PeLinkSetup.bEnablePeLink = TRUE; PeLinkSetup.PeCppiDioSel = CSL_AIF2_CPPI; PeLinkSetup.TddAxc = TRUE;//TDD mode ON PeLinkSetup.bEnObsaiBubbleBW = FALSE; PeLinkSetup.PeDelay = DB_PE_DELAY_OBSAI;//28 sys_clks delay between DB and PE for OBSAI PeLinkSetup.Crc8Poly = CRC8_POLY; PeLinkSetup.Crc8Seed = CRC8_SEED; //AT link setup AtLinkSetup.PE1Offset = 300; AtLinkSetup.PE2Offset = 310; AtLinkSetup.DeltaOffset = 370;// Packet DMA delay + pe1 + pe2 = 300 + 10 + 60 (min Delta) AtLinkSetup.PiMin = 370; AtLinkSetup.PiMax = 390; AtLinkSetup.IsNegativeDelta = FALSE;//positive delta /************** Common Setup ********************************************************************************/ //SD common setup SdCommonSetup.bEnablePllB8 = TRUE; SdCommonSetup.CLKBYP_B8 = CSL_AIF2_PLL_CLOCK_NO_BYPASS; SdCommonSetup.LB_B8 = CSL_AIF2_PLL_LOOP_BAND_MID;//High BW is also fine SdCommonSetup.VoltRangeB8 = CSL_AIF2_PLL_VOLTAGE_LOW;//fixed factor SdCommonSetup.SleepPllB8 = CSL_AIF2_PLL_AWAKE; SdCommonSetup.pllMpyFactorB8 = CSL_AIF2_PLL_MUL_FACTOR_25X;//for OBSAI when reference clock is 122.88 Mhz SdCommonSetup.SysClockSelect = CSL_AIF2_SD_BYTECLOCK_FROM_B8; SdCommonSetup.DisableLinkClock[0] = FALSE;//enable link0 clock //PD common setup PdCommonSetup.PdCppiDioSel = CSL_AIF2_CPPI;//AxC data uses CPPI for DMA machine PdCommonSetup.AxCOffsetWin = AXC_OFFSET_WIN;//AxC offset window PdCommonSetup.PdRadtTC = 3071999;//Terminal count value for RadT OBSAI frame time PdCommonSetup.PdFrameTC[0].FrameIndexSc = 0;//start index PdCommonSetup.PdFrameTC[0].FrameIndexTc = 6;//teminal index PdCommonSetup.PdFrameTC[0].FrameSymbolTc = 139;//140 Normal cyclic prefix symbols in one rad frame. PdCommonSetup.PdRoute[0].RouteTs = 0;//Route OBSAI time stamp for channel 0 PdCommonSetup.PdRoute[0].RouteType = OBSAI_TYPE_LTE;//Route OBSAI type for channel 0 PdCommonSetup.PdRoute[0].RouteAddr = 0;//Route OBSAI address for channel 0 PdCommonSetup.PdRoute[0].RouteLink = CSL_AIF2_LINK_0;//Route link for channel 0 PdCommonSetup.PdRoute[0].RouteMask = CSL_AIF2_ROUTE_MASK_NONE;//Route TS mask for channel 0 PdCommonSetup.PdChConfig[0].bChannelEn = TRUE;//Channel enable for channel 0 PdCommonSetup.PdChConfig[0].DataFormat = CSL_AIF2_LINK_DATA_TYPE_NORMAL;//Data format for channel 0 PdCommonSetup.AxCOffset[0] = 310;// same to Egress AxC offset PdCommonSetup.PdChConfig1[0].bTsWatchDogEn = FALSE;//disable watchdog for channel 0 PdCommonSetup.PdChConfig1[0].DataFormat = CSL_AIF2_GSM_DATA_OTHER;//Non GSM data PdCommonSetup.PdChConfig1[0].FrameCounter = 0;//OBSAI framing counter group number for channel 0 PdCommonSetup.PdChConfig1[0].TddEnable = 0xFFFF; PdCommonSetup.TddEnable1[0] = 0xFFFFFFFF;//enables all symbols(FDD) PdCommonSetup.TddEnable2[0] = 0xFFFFFFFF;//enables all symbols(FDD) PdCommonSetup.TddEnable3[0] = 0xFFFFFFFF;//enables all symbols(FDD) PdCommonSetup.TddEnable4[0] = 0xFFFFFFFF;//enables all symbols(FDD) PdCommonSetup.PdFrameMsgTc[0] = 551;//OBSAI frame message terminal count for first normal cyclic prefix symbol for(i=1;i<7;i++) PdCommonSetup.PdFrameMsgTc[i] = 547;//OBSAI frame message terminal count for ohter 6 normal cyclic prefix LTE symbols //PE common setup PeCommonSetup.PeTokenPhase = 0;//Phase alignment for scheduling DMA OBSAI: only lsb is used PeCommonSetup.EnetHeaderSelect = 1;//bit order for Ethernet preamble and SOF PeCommonSetup.PeFrameTC[0].FrameIndexSc = 0;//start index PeCommonSetup.PeFrameTC[0].FrameIndexTc = 6;//teminal index PeCommonSetup.PeFrameTC[0].FrameSymbolTc = 139;//140 normal cyclic prefix symbols in one rad frame. PeCommonSetup.bEnableCh[0] = TRUE;//Enable PE channel for channel 0 PeCommonSetup.PeDmaCh0[0].bCrcEn = FALSE;//disable CRC for channel 0 PeCommonSetup.PeDmaCh0[0].FrameTC = 0;//use framing terminal count 0 for channel 0 PeCommonSetup.PeDmaCh0[0].RtControl = CSL_AIF2_PE_RT_INSERT;//use PE insert option for channel 0 PeCommonSetup.PeDmaCh0[0].CrcType = CSL_AIF2_CRC_16BIT;//CRC type for channel 0 PeCommonSetup.PeDmaCh0[0].isEthernet = FALSE;//AxC data PeCommonSetup.PeDmaCh0[0].CrcObsaiHeader = FALSE;//calculate OBSAI header CRC PeCommonSetup.PeInFifo[0].SyncSymbol = 0;//sync symbol offset for channel 0 PeCommonSetup.PeInFifo[0].MFifoWmark = 3;//Message FIFO water mark for channel 0 PeCommonSetup.PeInFifo[0].MFifoFullLevel = 5;//Message FIFO full level for channel 0 PeCommonSetup.PeAxcOffset[0] = 311;// PE2 + 1 PeCommonSetup.PeFrameMsgTc[0] = 551;//OBSAI frame message terminal count for first normal cyclic prefix LTE symbols for(i=1;i<7;i++) PeCommonSetup.PeFrameMsgTc[i] = 547;//OBSAI frame message terminal count for other 6 normal cyclic prefix LTE symbols PeCommonSetup.PeModuloTc[0].bEnableRule = TRUE; PeCommonSetup.PeModuloTc[0].RuleModulo = 0;//Setup modulo rule 0 Modulo PeCommonSetup.PeModuloTc[0].bRuleObsaiCtlMsg = FALSE; PeCommonSetup.PeModuloTc[0].RuleIndex = 0;//Setup modulo rule 0 index PeCommonSetup.PeModuloTc[0].RuleLink = CSL_AIF2_LINK_0;//Route egress modulo rule 0 to link 0 PeCommonSetup.PeChObsaiType[0] = OBSAI_TYPE_LTE;//OBSAI header type for channel 0 PeCommonSetup.PeChObsaiTS[0] = 0;//OBSAI header Time Stamp for channel 0 PeCommonSetup.PeChObsaiAddr[0] = 0;//OBSAI header address for channel 0 PeCommonSetup.PeChObsaiTsMask[0] = CSL_AIF2_ROUTE_MASK_NONE;//OBSAI header TS mask for channel 0 PeCommonSetup.PeChObsaiTsfomat[0] = CSL_AIF2_TSTAMP_FORMAT_NORM_TS;//OBSAI header TS format for channel 0 PeCommonSetup.PeObsaiPkt[0] = FALSE;//Select OBSAI AxC or packet mode for channel 0 PeCommonSetup.PeBbHop[0] = FALSE;//Take OBSAI address from CPPI PS bits for channel 0 //Dual bit map setup. PeCommonSetup.PeObsaiDualBitMap[0].DbmX = 1;//set X-1. we have total 2 AxC space but use only one AxC space PeCommonSetup.PeObsaiDualBitMap[0].DbmXBubble = 0;//OBSAI 4 AxC sample length bubble PeCommonSetup.PeObsaiDualBitMap[0].Dbm1Mult = 0;//set n-1 PeCommonSetup.PeObsaiDualBitMap[0].Dbm1Size = 0;//set n-1 PeCommonSetup.PeObsaiDualBitMap[0].Dbm1Map[0] = 0x0; PeCommonSetup.ChIndex0[0] = 0; //channel 0 PeCommonSetup.bEnableChIndex0[0] = TRUE;//Route egress channel 0 to modulo rule 0 //Ingress DB setup IngrDbSetup.bEnableIngrDb = TRUE; //Enable Ingress DB IngrDbSetup.bEnableChannel[0] = TRUE; //Enable Ingress DB channel 0 IngrDbSetup.IngrDbChannel[0].BaseAddress = AIF2_DB_BASE_ADDR_I_FIFO_0; //Set DB FIFO base address for channel 0 IngrDbSetup.IngrDbChannel[0].BufDepth = CSL_AIF2_DB_FIFO_DEPTH_QW32; //Set DB FIFO depth for channel 0 to 32 QW(Quad word) IngrDbSetup.IngrDbChannel[0].DataSwap = CSL_AIF2_DB_NO_SWAP; //No swap IngrDbSetup.IngrDbChannel[0].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change IngrDbSetup.IngrDbChannel[0].bEnablePsData = TRUE; //Enable 4 bytes PS data IngrDbSetup.IngrDbChannel[0].PacketType = 0; //User data //Egress DB setup EgrDbSetup.bEnableEgrDb = TRUE; //Enable Ingress DB EgrDbSetup.PmControl = CSL_AIF2_DB_PM_TOKEN_FIFO;//for normal packet performance EgrDbSetup.bEnableChannel[0] = TRUE; //Enable Egress DB channel 0 EgrDbSetup.EgrDbChannel[0].BaseAddress = AIF2_DB_BASE_ADDR_E_FIFO_0; //Set DB FIFO base address for channel 0 EgrDbSetup.EgrDbChannel[0].BufDepth = CSL_AIF2_DB_FIFO_DEPTH_QW32; //Set DB FIFO depth for channel 0 to 32 QW EgrDbSetup.EgrDbChannel[0].DataSwap = CSL_AIF2_DB_NO_SWAP; //No swap EgrDbSetup.EgrDbChannel[0].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change //AD Common setup AdCommonSetup.IngrGlobalEnable = TRUE; AdCommonSetup.EgrGlobalEnable = TRUE; AdCommonSetup.FailMode = CSL_AIF2_AD_DROP;//drop fail packet AdCommonSetup.IngrPriority = CSL_AIF2_AD_PKT_PRI; AdCommonSetup.EgrPriority = CSL_AIF2_AD_AXC_PRI; AdCommonSetup.Tx_QueNum = AIF2_BASE_TX_QUE_NUM;//base egress queue number setup to 512 //AT Common setup AtCommonSetup.PhySyncSel = CSL_AIF2_SW_SYNC;//Select SW sync for Phy timer trigger AtCommonSetup.RadSyncSel = CSL_AIF2_SW_SYNC; AtCommonSetup.SyncMode = CSL_AIF2_NON_RP1_MODE; AtCommonSetup.AutoResyncMode = CSL_AIF2_AUTO_RESYNC_MODE; AtCommonSetup.CrcMode = CSL_AIF2_AT_CRC_DONT_USE;//Do not use RP1 CRC in this test AtCommonSetup.PhytCompValue = 0; AtCommonSetup.AtInit.pPhyTimerInit = &PhyTimerInit; AtCommonSetup.AtInit.pRadTimerInit = &RadTimerInit; PhyTimerInit.ClockNum = 0; PhyTimerInit.FrameLsbNum = 0; PhyTimerInit.FrameMsbNum = 0; RadTimerInit.ClockNum = 0; RadTimerInit.SymbolNum = 0; RadTimerInit.FrameLsbNum = 0; RadTimerInit.FrameMsbNum = 0; AtCommonSetup.AtTerminalCount.pPhyTimerTc = &PhyTimerTc; AtCommonSetup.AtTerminalCount.pRadTimerTc = &RadTimerTc; PhyTimerTc.FrameLsbNum = FRAME_COUNT_TC_PHY_TIMER;//set phy Frame TC to 4095 PhyTimerTc.ClockNum = CLOCK_COUNT_TC_PHY_TIMER; //set phy clock TC to 3071999 RadTimerTc.FrameLsbNum = FRAME_COUNT_TC_LTE_FDD;//set LTE Frame TC to 4095 RadTimerTc.SymbolNum = 139; //set LTE Symbol TC to 139 RadTimerTc.LutIndexNum = 6; //set LTE LutIndex TC to 6 AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = 22079; // long symbol AtCommonSetup.AtTerminalCount.RadClockCountTc[1] = 21919; AtCommonSetup.AtTerminalCount.RadClockCountTc[2] = 21919; AtCommonSetup.AtTerminalCount.RadClockCountTc[3] = 21919; AtCommonSetup.AtTerminalCount.RadClockCountTc[4] = 21919; AtCommonSetup.AtTerminalCount.RadClockCountTc[5] = 21919; AtCommonSetup.AtTerminalCount.RadClockCountTc[6] = 21919; //AT Event setup (Event 7) AtEventSetup.AtRadEvent[7].EventSelect = CSL_AIF2_EVENT_7;//Select Event 7 AtEventSetup.AtRadEvent[7].EventOffset = 0; AtEventSetup.AtRadEvent[7].EvtStrobeSel = CSL_AIF2_RADT_SYMBOL;//event will occur every symbol time AtEventSetup.AtRadEvent[7].EventModulo = 22080; AtEventSetup.AtRadEvent[7].EventMaskLsb = 0xFFFFFFFF; AtEventSetup.AtRadEvent[7].EventMaskMsb = 0xFFFFFFFF; AtEventSetup.bEnableRadEvent[7] = TRUE;//Enable Event 7 /****** Do AIF2 HW setup (set all MMRs above) **********************************************************************/ CSL_aif2HwSetup(hAif2, &aif2Setup); ctrlArg = TRUE; hAif2->arg_link = CSL_AIF2_LINK_0;//Select link num //Enable Serdes loopback for link 0 CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_LINK_LOOPBACK, (void *)&ctrlArg); //Enable Tx/Rx of link 0 CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg); CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg); for(i=0;i<100;i++)asm (" NOP 9 ");//insert time delay for aif2 configuration completion //AT Arm timer CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_ARM_TIMER, (void *)&ctrlArg); //Trigger the SW debug frame sync CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DEBUG_SYNC, (void *)&ctrlArg); } void main(void) { Uint32 *temp; Uint16 testpass; Uint32 idx, idx2, value; MNAV_MonolithicPacketDescriptor *mono_pkt; printf("Beginning AIF2 OBSAI LTE 20 MHz TDD mode test:\n\n"); for(idx=0;idx<2000;idx++)asm (" NOP 9 ");//delay for printf not to block ISR execution enable_module(aif_pdctl, aif_mdctl);//Enable AIF2 module power int4_result = 0; Intc_config(); MNavigator_config();//multicore navigator configuration for LTE for(idx =0; idx < 14; idx++){ //push 14 packets into Tx queue for test tmp[idx] = pop_queue(MONO_TX_COMPLETE_Q); tmp[idx] &= 0xFFFFFFF0;//set DESC_SIZE field to zero mono_pkt = (MNAV_MonolithicPacketDescriptor *)tmp[idx]; //Create Mono packet (initialize non-zero fields) mono_pkt->type_id = MNAV_DESC_TYPE_MONO; mono_pkt->data_offset = MNAV_MONO_PACKET_SIZE + 4;//16 if((idx%7) == 0) mono_pkt->packet_length = 8832;//first symbol else mono_pkt->packet_length = 8768;//other six symbols mono_pkt->ps_flags = 1; mono_pkt->epib = 0; mono_pkt->psv_word_count = 1; // 4 byte PS field length mono_pkt->pkt_return_qnum = MONO_TX_COMPLETE_Q; mono_pkt->src_tag_lo = 0; //copied to .flo_idx of streaming i/f temp = (Uint32 *)(tmp[idx] + 16); if((idx%7) == 0){ for (idx2 = 0; idx2 < 2208; idx2 ++) temp[idx2] = (idx << 16)+ idx2; //payload data setup(first symbol) } else { for (idx2 = 0; idx2 < 2192; idx2 ++) temp[idx2] = (idx << 16)+ idx2; //payload data setup(other six symbols) } //Create PS data temp = (Uint32 *)(tmp[idx] + MNAV_MONO_PACKET_SIZE); temp[0] = (Uint32)(0x00008000 + (idx << 7));//add symbol number into PS field tmp[idx] |= 0x00000003;//set DESC_SIZE to 3 for AIF2 mono mode //push_queue(MONO_TX_Q, 1, 0, tmp[idx]); } Aif2_MNAV_Obsai_config();//Aif2 configuration for M navigator mode /***************************************************************** * Enable AIF and wait for completion. */ while(1) { asm (" NOP 5 "); asm (" NOP 5 "); if(int4_result > 160) { //AT disable all events and halt timer ctrlArg = TRUE; CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DISABLE_ALL_EVENTS, (void *)&ctrlArg); CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_HALT_TIMER, (void *)&ctrlArg); ctrlArg = FALSE;//disable AD scheduler and Rx, Tx Link CSL_aif2HwControl(hAif2,CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_GLOBAL, (void *)&ctrlArg); CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_GLOBAL, (void *)&ctrlArg); CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg); CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg); CSL_aif2Reset(hAif2);//reset all aif2 modules break; } } /***************************************************************** * Compare the data in the destination buffers. */ /* Compare the Monolithic packet data */ testpass = 1; for (idx = 0; idx < 14; idx ++)//three UL symbol place will be filled with zero { tmp[idx] = pop_queue(MONO_RX_Q); tmp[idx] &= 0xFFFFFFF0;// clean DESC_SIZE field temp = (Uint32 *)tmp[idx]; temp += 4; //skip pkt header and PS field (16 bytes) if((idx%7) == 0){ for (idx2 = 0; idx2 < 2208; idx2 ++)if (temp[idx2] != (idx << 16)+ idx2) { testpass = 0; } } else if((idx != 4)&&(idx != 5)&&(idx != 6)){ for (idx2 = 0; idx2 < 2192; idx2 ++)if (temp[idx2] != (idx << 16)+ idx2) { testpass = 0; } } push_queue(MONO_RX_FDQ, 1, 0, tmp[idx]); } if (testpass == 1) printf(" Test a) Monolithic Packet Data Send/Recv: PASS\n"); else printf(" Test a) Monolithic Packet Data Send/Recv: FAIL\n"); /* read the descriptor counts of the Monolithic queues. */ value = get_descriptor_count(MONO_TX_Q); if (value != 0) printf(" Test b1) Monolithic Packet Tx Descriptor Counts:%d FAIL\n",value); else printf(" Test b1) Monolithic Packet Tx Descriptor Counts:%d PASS\n",value); value = get_descriptor_count(MONO_TX_COMPLETE_Q); if (value != 13) printf(" Test b2) Monolithic Packet Tx Complete Descriptor Counts:%d FAIL\n",value); else printf(" Test b2) Monolithic Packet Tx Complete Descriptor Counts:%d PASS\n",value); value = get_descriptor_count(MONO_RX_Q); if (value != 2) printf(" Test b3) Monolithic Packet Rx Descriptor Counts:%d FAIL\n",value); else printf(" Test b3) Monolithic Packet Rx Descriptor Counts:%d PASS\n",value); value = get_descriptor_count(MONO_RX_FDQ); if (value != 14) printf(" Test b4) Monolithic Packet Rx Free Descriptor Counts:%d FAIL\n",value); else printf(" Test b4) Monolithic Packet Rx Free Descriptor Counts:%d PASS\n",value); printf("\nEnding AIF2 OBSAI LTE 20 MHz TDD mode test\n"); }
Regards,Albert
Hi,
FYI.
We have recently added CPRI LTE TDD mode to MCSDK AIF2LLD. I enclosed an engineering release of the upcoming update. You'll find in this package a README file describing how to update AIF2LLD in your environment and how to generate the test examples.
.\ti\drv\aif2\test\cpricheckrf\ltetddcheckrf.c is a LTE TDD example that works in loopback mode as well.
3247.AIF2LLD_C6670_1_0_0_16_prelim.zip
Best rgds/Seb.
