C6745 CPU pipeline stalled and the CPU is 'not ready' -- related to errata advisory 2.1.21?

Paul,

Since you asked about Advisory 2.1.4, why have you not implemented the priority workarounds for it? I assume that is what you mean when you say you "have not configured priorities." You need to do that, and we give you the code to do it.

You have implemented a workaround for Advisory 2.1.21, so that is taken care of.

Exactly what are the steps you go through to get to the "Trouble Reading Memory Block" message? That sounds like a message you would get after connecting rather than as part of failing to connect. Using CCS v3.3 means you are using a very old debug platform. It should work fine, but for example I do not have it installed; I do not even have CCSv4 installed anymore, for what it is worth.

But I doubt the CCS version is directly related to your problem. The most likely cause is something is going wrong in your GEL file from functions that are called automatically, probably OnTargetConnect() and the functions it calls. You can find out by commenting out the functions in OnTargetConnect() and see if the emulator will let you connect. Then you can call those functions manually and find out which one has the problem.

There could be a problem with your SDRAM devices or the clock to EMIFB, but those are just wild guesses without any more to go on than this.

So, please provide some more detail on the steps you are going through to get to that message, and put in the Advisory 2.1.4 workarounds so you will not have to worry about that part (not directly related, but you brought it up and we do not want you to continue to be worried about it).

Regards,
RandyP

Hi Randy,

I am not familiar with how to set priorities on the C6745.  The MSTPRI0-3 registers provide priorities 0-7 for several peripherals, but I am not sure that I use more than the EDMA3TC0 peripheral.  I have not been able to find any documentation on the CPUARBU register.  What are the constants in the errata advisory example (i.e., CPU_PRIORITY, MAST_PRI, MAST_SHIFT, etc.)?

In regards to the OnTargetConnect() GEL function, I execute the following commands:

// unload all symbols -- may help with CCS crashes relating to the message window?
GEL_UnloadAllSymbols();

// disable interrupts
IER = 0x0;
ICR = 0xFFFFFFFF;

// disable EDMA
EDMA_3CC_IECRH = 0xffffffff; // IERH - Disable high interrupts
EDMA_3CC_EECRH = 0xffffffff; // EERH - Disable high events
EDMA_3CC_ICRH = 0xffffffff; // ICRH - Clear high interrupts
EDMA_3CC_ECRH = 0xffffffff; // ICRH - Clear high events
EDMA_3CC_IECR = 0xffffffff; // IER - Disable low interrupts
EDMA_3CC_EECR = 0xffffffff; // EER - Disable low events
EDMA_3CC_ICR = 0xffffffff; // ICR - Clear low interrupts
EDMA_3CC_ECR = 0xffffffff; // ICRH - Clear low events

// enable EMIFB
PSC1_LPSC_enable(0, LPSC_EMIFB);
DEVICE_kickUnlock();
PINMUX0 = (PINMUX0 & ~0xFFFFFFF0) | 0x11111100;
PINMUX1 = (PINMUX1 & ~0xFFFFFFFF) | 0x11111111;
PINMUX2 = (PINMUX2 & ~0xFFFFFFFF) | 0x01111111;
PINMUX3 = (PINMUX3 & ~0xFFFFFFFF) | 0x00000000;
PINMUX4 = (PINMUX4 & ~0xFFFFFFFF) | 0x00000000;
PINMUX5 = (PINMUX5 & ~0xFFFFFFFF) | 0x11111110;
PINMUX6 = (PINMUX6 & ~0xFFFFFFFF) | 0x11111111;
PINMUX7 = (PINMUX7 & ~0x00000FFF) | 0x00000111;
EMIF3A_SDRCR |= SDRFC_LP_MODE | SDRFC_SR_PD;
EMIF3A_SDCR |= SDCFG_BOOT_UNLOCK | SDCFG_TIMUNLOCK;
EMIF3A_PBBPR = 0x20;
EMIF3A_SDTIMR1 = (t_RFC<<25) | (t_RP<<22) | (t_RCD<<19) | (t_WR<<16) | (t_RAS<<11) | (t_RC<<6) | (t_RRD<<3);
EMIF3A_SDTIMR2 = (t_RAS_MAX<<27) | (t_XSR<<16) | (t_CKE<<0);
EMIF3A_SDCR = SDCFG_SDREN | SDCFG_NM | SDCFG_CL_CAS2 | SDCFG_IBANK_4 | SDCFG_PAGESIZE_512;
EMIF3A_SDRCR = 780;

Most of this code originates from an evaluation board...

Thanks!
-Paul

Hi Paul,

The TMS320C674x DSP Megamodule Reference Guide (http://www.ti.com/lit/ug/sprufk5a/sprufk5a.pdf) should shed some light on how priorities work in the C6745 and provide insight into the CPUARBU register.

This information is contained in section 6 on the 'Bandwidth Management Architecture' (pg. 144). Specifically, the discussion on priorities begins in section 6.2 (pg. 145) and section 6.3 on registers (pg. 146) describes the CPUARBU register.

RandyP,

Thanks for the help on this issue. Can you comment on any of the feedback Paul provided?

Thanks,

Clinton

Paul,

The code to access the appropriate registers, for which Clinton has pointed to documentation, is included in the errata Advisory 2.1.4 work around section.

What are the exact steps you go through to reach the problem message, starting from powering the board?

What is the boot mode for the board? If it applies, is there a boot ROM that does initialization on the DSP at boot time?

That is a lot of initialization stuff to have in OnTargetConnect(). If this came from the EVM and you are running it on your own board, are the PINMUX settings still correct for your board?

Regards,
RandyP

It seems that the default priorities satisfy the errata.  The default priority of CPUARBU is 1 which does not equal any of the default priorities in MSTPRI0/1/2.  Regardless, I now set the priorities according to their defaults (attached).

#include <stdint.h>

#include "errorCode.h"
#include "priorities.h"

enum arbitrationPriority_e
{
	ARB_PRIORITY_0 = 0,
	ARB_PRIORITY_1 = 1,
	ARB_PRIORITY_2 = 2,
	ARB_PRIORITY_3 = 3,
	ARB_PRIORITY_4 = 4,
	ARB_PRIORITY_5 = 5,
	ARB_PRIORITY_6 = 6,
	ARB_PRIORITY_7 = 7
};

enum arbitrationMaxWait_e
{
	ARB_MAXWAIT_STALL       = 0x00,
	ARB_MAXWAIT_1_CYCLE     = 0x01,
	ARB_MAXWAIT_2_CYCLES    = 0x02,
	ARB_MAXWAIT_4_CYCLES    = 0x04,
	ARB_MAXWAIT_8_CYCLES    = 0x08,
	ARB_MAXWAIT_16_CYCLES   = 0x10,
	ARB_MAXWAIT_32_CYCLES   = 0x20
};

static void _setPriority_CPUARB(uint32_t *CPUARB, enum arbitrationPriority_e pri, enum arbitrationMaxWait_e maxwait);
static void _setPriority_IDMAARB(uint32_t *IDMAARB, enum arbitrationMaxWait_e maxwait);
static void _setPriority_SDMAARB(uint32_t *SDMAARB, enum arbitrationMaxWait_e maxwait);
static void _setPriority_UCARB(uint32_t *UCARB, enum arbitrationMaxWait_e maxwait);
static void _setPriority_MDMAARB(uint32_t *MDMAARB, enum arbitrationPriority_e pri);
static void _setPriority_MSTPRI0(enum arbitrationPriority_e DSP_MDMA, enum arbitrationPriority_e DSP_CFG);
static void _setPriority_MSTPRI1(enum arbitrationPriority_e PRU0, enum arbitrationPriority_e PRU1, enum arbitrationPriority_e EDMA3TC0, enum arbitrationPriority_e EDMA3TC1);
static void _setPriority_MSTPRI2(enum arbitrationPriority_e EMAC, enum arbitrationPriority_e USB0CFG, enum arbitrationPriority_e USB0CDMA, enum arbitrationPriority_e UHPI, enum arbitrationPriority_e USB1, enum arbitrationPriority_e LCDC);
static void _setPriority_L1D(void);
static void _setPriority_L2(void);
static void _setPriority_EMC(void);
static void _setPriority_MSTPRI(void);






BSL_errorCode_t BSL_initPriorities(void)
{
	_setPriority_L1D();
	_setPriority_L2();
	_setPriority_EMC();
	_setPriority_MSTPRI();

	return BSL_SUCCESS;
}

void _setPriority_CPUARB(uint32_t *CPUARB, enum arbitrationPriority_e pri, enum arbitrationMaxWait_e maxwait)
{
	(*CPUARB) = ((pri & 0x7) << 16) | (maxwait & 0x3F);
}

void _setPriority_IDMAARB(uint32_t *IDMAARB, enum arbitrationMaxWait_e maxwait)
{
	(*IDMAARB) = (maxwait & 0x3F);
}

void _setPriority_SDMAARB(uint32_t *SDMAARB, enum arbitrationMaxWait_e maxwait)
{
	(*SDMAARB) = (maxwait & 0x3F);
}

void _setPriority_UCARB(uint32_t *UCARB, enum arbitrationMaxWait_e maxwait)
{
	(*UCARB) = (maxwait & 0x3F);
}

void _setPriority_MDMAARB(uint32_t *MDMAARB, enum arbitrationPriority_e pri)
{
	(*MDMAARB) = ((pri & 0x7) << 16);
}

void _setPriority_MSTPRI0(enum arbitrationPriority_e DSP_MDMA, enum arbitrationPriority_e DSP_CFG)
{
	*((uint32_t *)0x01C14110) = 0x44440022 | ((DSP_MDMA & 0x7) << 8) | ((DSP_CFG & 0x7) << 12);
}

void _setPriority_MSTPRI1(enum arbitrationPriority_e PRU0, enum arbitrationPriority_e PRU1, enum arbitrationPriority_e EDMA3TC0, enum arbitrationPriority_e EDMA3TC1)
{
	*((uint32_t *)0x01C14114) = 0x44440000 | ((PRU0 & 0x7) << 0) | ((PRU1 & 0x7) << 4) | ((EDMA3TC0 & 0x7) << 8) | ((EDMA3TC1 & 0x7) << 12);
}

void _setPriority_MSTPRI2(enum arbitrationPriority_e EMAC, enum arbitrationPriority_e USB0CFG, enum arbitrationPriority_e USB0CDMA, enum arbitrationPriority_e UHPI, enum arbitrationPriority_e USB1, enum arbitrationPriority_e LCDC)
{
	*((uint32_t *)0x01C14118) = 0x0 | ((EMAC & 0x7) << 0) | ((USB0CFG & 0x7) << 8) | ((USB0CDMA & 0x7) << 12) | ((UHPI & 0x7) << 20) | ((USB1 & 0x7) << 24) | ((LCDC & 0x7) << 28);
}

void _setPriority_L1D(void)
{
	_setPriority_CPUARB( (uint32_t *)0x01841040, ARB_PRIORITY_1, ARB_MAXWAIT_16_CYCLES);
	_setPriority_IDMAARB((uint32_t *)0x01841044, ARB_MAXWAIT_16_CYCLES);
	_setPriority_SDMAARB((uint32_t *)0x01841048, ARB_MAXWAIT_1_CYCLE);
	_setPriority_UCARB(  (uint32_t *)0x0184104C, ARB_MAXWAIT_32_CYCLES);
}

void _setPriority_L2(void)
{
	_setPriority_CPUARB( (uint32_t *)0x01841000, ARB_PRIORITY_1, ARB_MAXWAIT_16_CYCLES);
	_setPriority_IDMAARB((uint32_t *)0x01841004, ARB_MAXWAIT_16_CYCLES);
	_setPriority_SDMAARB((uint32_t *)0x01841008, ARB_MAXWAIT_1_CYCLE);
	_setPriority_UCARB(  (uint32_t *)0x0184100C, ARB_MAXWAIT_32_CYCLES);
}

void _setPriority_EMC(void)
{
	_setPriority_CPUARB( (uint32_t *)0x01820200, ARB_PRIORITY_1, ARB_MAXWAIT_16_CYCLES);
	_setPriority_IDMAARB((uint32_t *)0x01820204, ARB_MAXWAIT_16_CYCLES);
	_setPriority_SDMAARB((uint32_t *)0x01820208, ARB_MAXWAIT_1_CYCLE);
	_setPriority_MDMAARB((uint32_t *)0x0182020C, ARB_PRIORITY_7);
}

void _setPriority_MSTPRI(void)
{
	_setPriority_MSTPRI0(ARB_PRIORITY_2, ARB_PRIORITY_2);
	_setPriority_MSTPRI1(ARB_PRIORITY_0, ARB_PRIORITY_0, ARB_PRIORITY_0, ARB_PRIORITY_0);
	_setPriority_MSTPRI2(ARB_PRIORITY_4, ARB_PRIORITY_4, ARB_PRIORITY_4, ARB_PRIORITY_6, ARB_PRIORITY_4, ARB_PRIORITY_5);
}

We cannot cause a condition to reproduce the problem at this time.  It just happens once in awhile.  We're using our own board with the C6745 PTP part configured to boot over SPI flash.  The PINMUX registers are set correctly for our board in code, the GEL file, and AIS boot script.

Hi Paul,

If the problem reappears, please post and let us know any additional information that could help us address the issue. If there are any other related questions you have, please let us know.

Thanks,

Clinton