• State Resolved
  • Locked Locked
  • Replies 14 replies
  • Answers 4 answers
  • Subscribers 99 subscribers
  • Views 1539 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C5505 Clock jitter

Diane Lim
Prodigy 250 points

Hi,

I'm working on a C5505 with an external 12MHz and 32.768KHz Quartz.

My application requires the least clock jitter (almost 100 ppm) and i want to set the SysClock at 128MHz.

I have observed that if i clock the system from the 32,768KHz, using the PLL for generating 128Mhz, the clock is stable (observation from a signal analyzer).

But, i don't get a round value (128.024MHz). It is imporant for my application to get exactely 128Mhz that why i want to use the 12 Mhz and expect the same stability.

When I used the 12Mhz, i observed a big jitter, almost a variation of 5Mhz.

I don't understand why i lost lot of stability with the 12 Mhz unlike with the 32.768Khz. Have you an idea ?

To get the 128Mhz with the 12 Mhz, i put a divider to get close to 170KHz as possible (limit of the PLL input): it is a suggestion for minimizing the jitter in a post.

On below my configuration of PLL:

CGCR1 = 0x0173,

CGICR = 0x0047,

CGCR2 = 0x0806,

CGOCR = 0x0000

Do you think that I can put a 32KHz as input of RTC clock instead of a 32.768Khz ? It allows me to get an exact 128MHz.

Thanks for your support.

Diane

  • 0
    TI__Mastermind 23785 points

    Please refer to Table 6-1 for the RTC Oscillator crystal requirements. We have not characterized the min and max specification. However, a slight variance is allowed.

    Section 6.5.2 talks about external clock source requirements.

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 250 points

    Hi Steve,

    Ok for the 32Khz, i will test it.

    For external clock requirements, the power supply is clean and the 12Mhz quartz (ASV from ABRACON) is stable.

    I don't undrestand why the 128Mhz is not stable at the PLL's output. 

    I did'nt have this problem when the PLL is sourced by the 32.768Khz.

    Can you explain it ?

    I'm wondering if it is caused by the divider at the PLL's entry (the 32.768Khz is directly put at the PLL's input instead that the 12Mhz has to be divided for the PLL's entry).

    Thanks.

    Diane

  • 0 in reply to Diane Lim
    TI__Mastermind 23785 points

    Are you using the 12 MHz crystal to drive the RTC_XI pins instead of the 32.768 KHz?

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 250 points

    No, the 12Mhz is used on the CLKIN and 32.768Khz is used for the RTC clock.

    My PLL can be sourced by the CLKIN or the RTC_CLK, by setting the CLKSEL (and executing the corresponding program).

    Best regards,

    Diane

  • 0 in reply to Diane Lim
    TI__Mastermind 23785 points

    Can you do a quick check with PLL in bypass mode to compare the in/out of the 12MHz; and try a 128MHz to CLKIN.

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 250 points

    Hi,

    I have checked the 12Mhz and it is stable.

    For the 128Mhz, you mean to put directly a 128Mhz to the CLKIN ? But the CLKIN is limited to 24 Mhz (refer to the datacheet on chapter 6.4.2).

    Best regards

  • 0 in reply to Diane Lim
    TI__Mastermind 23785 points

    You are right about the 24MHz. Now that you have checked out the PLL bypass mode. You can try out the PLL divider values or using the 32KHz clock to generate the 128MHz clock you want. Would this resolve your question?

    Regards.

  • 0 in reply to Steve Tsang
    Prodigy 250 points

    I haven't the 32Khz quartz ready. I will receive it in few days.

    What do you mean by traying out the PLL divider values ?

    I have tried to generate the 128Mhz from the 12Mhz (at my first post, i have described PLL register configuration).

    There is other possible divider and multiplier configuration, but it doesn't change the result: the 128 Mhz is obtained but it is not stable.

    From the 32.768Khz, the generated 128.03Mhz is stable. The difference between these 2 configurations is that the 32.768Khz is only multiplied, whereas the 12Mhz has to be divided before multiplying.

  • 0 in reply to Diane Lim
    TI__Mastermind 30140 points

    Hi Diane,

    Please try these register settings...

    Given CLKSEL = 1 & 12 MHz @ CLKIN, use the following PLL reg settings for 128MHz:

    PLL_CNTL1 (IOaddress=0x1C20)    0x831C
    PLL_CNTL2 (IOaddress=0x1C21)    0x0047
    PLL_CNTL3 (IOaddress=0x1C22)    0x0806
    PLL_CNTL4 (IOaddress=0x1C23)    0x0000

    f_PLLIN = 160 kHZ

    f_PLLOUT = 128 MHz

    Verified stable on my C5515 EVM.

    Are you clocking the C5515 > 120 MHz? Not meant to.. The C5505 has a 150 MHz variant (TMS320C5505AZCH15) that we test at 150 MHz operation (CVDD and VDDA_PLL must be supplied with 1.4V).

    Hope this helps,
    Mark

  • 0 in reply to Mark M
    Prodigy 250 points

    Hi Mark,

    Have you modified the C5515 EVM board for getting CLKSEL = 1 & 12 MHz @ CLKIN ? Because i see that the C5515 EVM is only sourcing by the 32.768KHz.

    I use my own breadboard for clocking to 128Mhz with a C5505.

    I get the 2 variants of C5505 and i don't observe a difference: the clock is varying between 126.05 and 131.88 Mhz. I have 2 boards: one with a variant 12 and an another with a variant 15. Both are supplied with 1.4V.

    My PLL register settings for 128 Mhz are almost the same (i set the PLL_CNTL1 0x031C instead of 0x831C, probably because of using the C5505).

    Can you precise me the accurancy ratio of your 128Mhz ?

    Best regards,

    Diane

  • 0 in reply to Diane Lim
    TI__Mastermind 30140 points

    Hi Diane,

    I am using the C5515 EVM, which has a jumper for CLK_SEL and a socket for crystal oscillators to supply CLKIN
    TI Page: http://www.ti.com/tool/tmdxevm5515
    Spectrum Digital Page: http://support.spectrumdigital.com/boards/evm5515/revb

    Are you referring to the C5515 eZdsp?
    TI Page: http://www.ti.com/tool/tmdx5515ezdsp
    Spectrum Digital Page: http://support.spectrumdigital.com/boards/usbstk5515/

    I have taken the following measurements from the CLKOUT pin... Jitter is small...

    When I used PLL_CNTL1 0x031C instead of 0x831C, I observed the incorrect PLL frequency and strange behavior with the frequency reducing over time...

    In both C5505 and C5515 System User Guide, bit 15 of PLL_CNTL1 (CGCR1) [1C20h] is reserved - "This bit must be set to 1 for normal operation"

    While debugging new boards before, I have seen high jitter at the CLKOUT pin... It was resolved by dampening the CLKIN signal with a 50ohm resistor in series to reduce transmission line reflections...

    Hope this helps,
    Mark

  • 0 in reply to Mark M
    Prodigy 250 points

    Hi Mark,

    Thanks a lot, you clarify me.

    1) I didn't see that the C5515 EVM can be sourced by the 12Mhz (I belived that it was only used for the USB clock and don't the link with the CLKIN on schematics).

    I try to use the C5515 EVM with CLK_SEL=1 (thank to the jumper), but my gel file is not good (I have a connecting error to the target). I try to modify it quickly with no success.

    Can I get a gel file with the CLK_SEL=1 configuration ?

    2) You are right, the bit 15 of PLL_CNTL1 (CGCR1) must be set to 1. I didn't notice it because it is a reserved bit wit 0 value.

    Until now, all my PLL configurations are setting with this bit at 0. I have corrected it, but there is no progress (the clock is still unstable).

    3) Your solution with the 50ohm resistor in series, i'm investigating it.

    Best regards,

    Diane

  • 0 in reply to Diane Lim
    TI__Mastermind 30140 points

    Hi Diane,

    You can use the PLL calculator to generate the register values for your PLL: http://ap-fpdsp-swapps.dal.design.ti.com/index.php/File:C5517_C5537_PLL_Calculator.xlsx

    I believe this PLL calculator was designed only for the 120MHz devices, and it will report out of range error for any PLL frequency higher than 120MHz. Reading the C5505 datasheet, you know that the 150MHz version for the C5505 device can reach PLL frequencies up to 150 MHz if 1.4V is supplied to VDDA_PLL and CVDD.

    http://ap-fpdsp-swapps.dal.design.ti.com/index.php/File:C5517_C5537_PLL_Calculator.xlsx

    I have attached the GEL file I use to get 128MHz from 12MHz CLKIN with CLK_SEL = 1...
    1440.C5515 forum just 128mhz CLKSEL 1.gel

    If you try to use the PLL register settings created for the 32768 Hz RTC clock, but you use CLK_SEL = 1 and CLKIN = 12MHz, then the PLL will be in a bad operating condition.

    Hope this helps,
    Mark

  • 0 in reply to Mark M
    Prodigy 250 points

    Hi Mark,

    I found what's the problem: on my board, we have put a filter on output of 12Mhz.

    When we remove the capacitor, leaving only a resitor in series, the clock is now stable.

    I suppose that the DSP already includes a capacitor (a filter) inside, that is right ?

    Best regards and thanks,

    Diane