Other Parts Discussed in Thread: OMAP-L138
We have a custom board application using the OMAP-L138. The ROM boot revision is d800k006. We have a small custom boot loader that, in theory, could fit entirely into the L1P and L1D memory of the DSP. If possible, I would like to run this without any caching to have full determinism.
Right now, I have a strange trick that uses the AISGen tool to set the PLL, PSC, and Flash CS2 register to load the DSP program from flash to L2 DSP memory, then jump to our ARM code. The ARM sets a bit more hardware and wakes the DSP officially after setting the start address. This much works fine. I am also able to turn the L1P and L1D caching feature off by setting the registers in the TMS320C674x DSP Megamodule Reference Guide (sprufk5a), sections 2.4, 3.4, and 4.4 (though L2 starts as full RAM). The code is noticeably slower once I do this, so I am assuming caching is now off.
Unfortunately, section 2.9 of the same document points out that even once it becomes RAM, the CPU cannot load or store anything to L1P RAM, and is strictly limited to instruction fetch. This would work for us, if we had any way to get the instructions there in the first place.
1. Is there any way for the AIS Bootloader to access the L1P RAM? Linking the code at the memory mapped address for L1P does not result in correct functionality. (Mapped to everyone at 0x11E00000, not just the DSP)
2. Is there an easy method for the ARM to move a DSP code image into the DSP L1P cache using a copy table or some other linker generated magic? Am I only limited to using the EDMA or IDMA as the DSP documentation suggests?
3. Is there any way for the ARM itself to turn off caching of the DSP? I have not been able to access the DSP memory System (mapped only to the DSP) from the ARM. I have compromised in that the DSP turns off caching as soon as it starts, but I have no way of knowing if these instructions are themselves cached.
In order to turn off cache, I am setting the lower three bits (2-0) in the following registers to 0 (cache disabled)
01840020h L1PCFG
01840040h L1DCFG
01840000h L2CFG
