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Run-time overhead of Memory Protection on C6678

We have just enabled hardware memory protection of the MSMC memory using (a) the XMC-MPAX unit in the CorePAC to prevent accidental overwrite of code and read-only data, etc. and (b) done roughly the same using the SMS-MPAX unit in MSMC to do the same thing for accesses by the PCIe and SRIO peripherals, etc.

We noticed that the throughput of our system degraded by about 1%. We were not expecting that. Can someone please explain if this should have been expected.

Regards, Jonathan

  • Hi Jonathan,

    I have been discussing this with out internal teams and we were wondering how your system is accessing the MSMC RAM – by direct address (0x0C00_0000 – 0x0CFF_FFFF) or aliased addressing.  Note that direct address are placed in the “Fast RAM” path. If you are using aliased addressing to MSMC RAM, you will incur 1 extra cycle of latency.

    This is documented in the CorePac user guide, search for Fast RAM, here is the cut-paste from the UG.

  • Hi Juan, I should have mentioned that there is no address aliasing at all in this scenario. We are only using XMC MPAX to alter permissions.

    Basically we use a low-numbered XMC MPAX segment (segment 3) to make all 4MBytes of MSMC an illegal access, then we selectively allow execute access to the code area for the core in question, and all-access for the data area for the core in question, using higher-numbered segments.

    So I believe we should always be on the fast RAM path, and would still like to understand the slow-down.

    Regards, Jonathan

  • There should be no slow down from MPAX used to simply implement memory protection. Maybe you can provide some details such as what was being measured before and after and what else changed. Did any memory locations change for example, did something change from a boundary being align to non-aligned. How much data is this being measured on. How measurements being performed.