DDR2, DDR3, DDR_CK and M_CLK

Patrick Ruf

Other Parts Discussed in Thread: SYSBIOS, AM3359

Hello,

I try to figure out what memory would be the best solution for a AM335x target board. Therefore I studied the various schematics of the AM335x boards and the AM335x ARM Technical manual and the Datasheet.

Questions:

1. EMIF M_CLK max. (section 7.3.2.2 of AM335x technical manual)
In the technical manual it is written that the maximum M_CLK is 100MHz. As I can see from AM335x ICE board GEL file (from SYSBIOS Ind SDK) the DDR PLL is configured with M=303, N=23 and M2=1 (DDR_PLL_Config( CLKIN, 23, 303, 1);). In my opinion this results in a M_CLK of 151.5MHz. What about the 100MHz maximum? Am I wrong?

2. AM335x ICE uses DDR2 SDRAM. How comes that the GEL files configures the DDR to a frequency of 303MHz. The AM335X datasheet says DDR_CK maximum is 266MHz with DDR2 (section 5.5.2.2.1).

3. Is it possible that in the figure 8-7 (ADPLLS) there is a mistake because of the "1/2 (1Bit)" Block in the CLKOUT path?
In Table 8-15 it is written that CLKOUT=[M / (N+1)] * CLKINP * [1/M2]. There is no "1/2"?

4. In newer AM335x schematics (like the new AM335x Starter Kit) TI uses DDR3 SDRAM instead of DDR2 SDRAM. What is the reason? Speed? Availability or Price? What does TI recommend for a new industrial design?

Any information to this questions are highly appreciated. Thanks.

Best regards,
Patrick

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi Patrick,

The AM335X supports DDR2 at clock rate up to 266MHz clock rate and DDR3 at up to 303MHz. These are the external clocks that drive the memory chips. Choice of memory is entirely up to you. Speed, availability and price are decision factors for sure. Another factor may be design complexity - DDR3 is slightly more complex than DDR2. Here are a couple of links on DDR at the TI wiki pages:

http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

If you search the wiki you'll probably find more information.

0 Patrick Ruf over 12 years ago in reply to Biser Gatchev-XID

Genius 4900 points

Hi Biser,

Thanks for your answers. Why does TI configure the DDR2 SDRAM on the ICE board with 303MHz, if max. frequency of DDR2 is 266MHz? Maybe I'm wrong with my interpretation of the ADDPLLS and how the clocks are routed. Maybe TI can explain in more detail my questions.

Thanks.
Patrick

0 Patrick Ruf over 12 years ago in reply to Patrick Ruf

Genius 4900 points

Hello

Also there are slight differences between DDR2 initialisation in TI Starterware Bootloader (used in AM335x Ind. SDK V1.0.0.5) and the GEL file for ICE board used in AM335x Ind. SDK V1.0.0.5.

Differences found so far are: (related to names used in GEL file, unfortunately not the same as used in Bootloader)
- DDR2_PHY_RD_DQS_SLAVE_RATIO_DEFINE (0x12 versus 0x40)
- DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO_DEFINE (0x80 versus 0x56)
- PHY_DLL_LOCK_DIFF_DEFINE (0x0 versus 0x4)
- DDR2_SDRAM_TIMING1 (0x0666B3C9 versus 0x0666B3D6)
- DDR2_SDRAM_TIMING2 (0x243631CA versus 0x143731DA)
- DDR2_SDRAM_TIMING3 (0x00000337 versus 0x00000347)

Maybe these differences come from different clocking.

As we are new to DDR2 technology we have to rely on information especially found in a Starterware package. Would be more helpfull if information is more consistent.

As for example in GEL file the DDR2_REF_CTRL is set to 0x0000081a. This means @266MHz Clock the refresh rate correspond to the average periodic refresh (commercial, 7.8us) found in the datasheet of the used DDR2 SDRAM (MT47H128M16RT-25E). But if the clock is 303MHz this should be set to 0x0000093B.

Can someone from TI please check this and confirm which timing and clocking is the right one for the AM335x ICE board?

Right now we are in the decision process choosing DDR2 or DDR3 SDRAM. And this question is related to the speed as well.

Thanks.

Patrick

0 Biser Gatchev-XID over 12 years ago in reply to Patrick Ruf

TI__Guru**** 393215 points

Hi Patrick,

There is a tuning procedure for the DDR memory, which is board dependent. You can find it at this link: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

0 Patrick Ruf over 12 years ago in reply to Biser Gatchev-XID

Genius 4900 points

Hi Biser,

Can you please be a bit more specific to the questions. In the first post I ask why is the GEL file cloking the DDR2 RAM with 303MHz although the max frequency is 266MHz. Then I can see that the Bootloader clocks with 266MHz. Now I can see that the refresh rate of the GEL file is wrong if clocked with 303MHz.

I use the AM335x ICE board from TI and I think I don't have to tune the board with a correct refreash rate?!

I know all this documents exist on processors.wiki.

Regards,
Patrick

0 Biser Gatchev-XID over 12 years ago in reply to Patrick Ruf

TI__Guru**** 393215 points

Hi Patrick,

Sorry, I lost the thread beginning. Which GEL file are you talking about? If it's the one from Starterware, this is for the Starter Kit, which comes with DDR3 memory. I don't think any GEL files are used for determining DDR2 parameters.

0 Patrick Ruf over 12 years ago in reply to Biser Gatchev-XID

Genius 4900 points

Hi Biser,

The GEL file is from Ind SDK V1.0.0.5 found under C:\TI\am335x_sysbios_ind_sdk_1.0.0.5\sdk\tools\gel\ICE
From the name of the file I expect this is for ICE board.

DDR PLL is set to 303MHz:

hotmenu ARM_OPP100_Config()
{
GEL_TextOut("**** AM335x ALL PLL Config for OPP == OPP100 is in progress ......... \n","Output",1,1,1);
GetInputClockFrequency();
if(CLKIN==24)
{
   MPU_PLL_Config( CLKIN, 23, 550, 1);
   CORE_PLL_Config( CLKIN, 23, 1000, 10, 8, 4);
   DDR_PLL_Config( CLKIN, 23, 303, 1);
   PER_PLL_Config( CLKIN, 23, 960, 5);
   DISP_PLL_Config( CLKIN, 23, 48, 1);
   GEL_TextOut("**** AM335x ALL ADPLL Config for OPP == OPP100 is Done ......... \n","Output",1,1,1);
}
else
   GEL_TextOut("**** AM335x PLL Config failed!! Check SYSBOOT[15:14] for proper input freq config \n","Output",1,1,1);
}

But DDR RAM parameters are for 266MHz:
//##############################################################################
//##############################################################################
//                       DDR Configuration Section
//##############################################################################
//##############################################################################

//******************************************************************
//DDR2=266MHz
//OPP100
//******************************************************************

//globals
#define DATA_MACRO_0 0
#define DATA_MACRO_1 1

//*******************************************************************
//DDR2 PHY parameters
//*******************************************************************
#define DDR2_REG_PHY_CTRL_SLAVE_RATIO_DEFINE      0x80
#define DDR2_PHY_RD_DQS_SLAVE_RATIO_DEFINE        0x12
#define DDR2_PHY_WR_DQS_SLAVE_RATIO_DEFINE        0
#define DDR2_REG_PHY_WRLVL_INIT_RATIO_DEFINE      0
#define DDR2_REG_PHY_GATELVL_INIT_RATIO_DEFINE    0
#define DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO_DEFINE   0x80
#define DDR2_REG_PHY_WR_DATA_SLAVE_RATIO_DEFINE   0x40
#define DDR2_PHY_DLL_LOCK_DIFF_DEFINE             0x0
#define DDR2_PHY_INVERT_CLKOUT_DEFINE             0x0

#define PHY_REG_USE_RANK0_DELAY                   0x01
#define CMD_REG_PHY_CTRL_SLAVE_DELAY_DEFINE       0x00
#define CMD_REG_PHY_CTRL_SLAVE_FORCE_DEFINE       0x00
#define PHY_DLL_LOCK_DIFF_DEFINE                  0x0

#define DDR_IOCTRL_VALUE (0x18B)

and do not correspond to parameters set in Ind SDK Bootloader found under C:\TI\am335x_sysbios_ind_sdk_1.0.0.5\sdk\starterware\bootloader\src.

Regards,
Patrick

TMDXICE3359.gel

0 Frank Walzer over 12 years ago in reply to Patrick Ruf

TI__Mastermind 44116 points

Patrick,

by mistake this version of the GEL was added to IA-SDK 1.0.0.5. Clearly the current ICE board only has DDR2 and therefor 303MHz is an unsupported option. It seems to work for standard environment so it didn't show up as a failure during tests. But obviously we can't use that file any more and I would recommend all IA-SDK users to replace the version with the latest one on the processor wiki. We will also change that for the next IA-SDK rev.

Also we need to look into the other issues you are questioning on the current GEL file. I assume our team in US to work on this and to update the processor wiki again if required. IA-SDK will then merge that version. I agree that IA-SDK boot code also should match the GEL environment as otherwise all the testing may be invalid if done in emulator setup only. However as boot code and GELs can also be changed by customers (and usually has to be done for custom hardware anyway) this is an area partially outside of our control.

Regards,

0 Patrick Ruf over 12 years ago in reply to Frank Walzer

Genius 4900 points

Frank,

Thanks. I fully agree. If I design my own board I of course have to write my own GEL file and bootloader. But to reduce risk probably most customers try to lean on current designs and therefore have to rely on those informations. Work into the whole topic is already a difficult task.

I just tried to find the correct GEL file but no success so far. I just found an other wrong file under http://processors.wiki.ti.com/index.php/AM335xBoards.

Can you give me link to the correct one? Thanks.

Best regards,
Patrick

0 Frank Walzer over 12 years ago in reply to Patrick Ruf

TI__Mastermind 44116 points

See this: http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x

Regards.

0 Jeff Mullins over 12 years ago in reply to Frank Walzer

Prodigy 20 points

Just to tag onto this. On Nov 14th, I posted this about the ICE EMIF config in the GEL file being incorrect. ICE looks to be 50 ohm termination for DDR2, but the GEL config specifies 75 ohm. When we copied the ICE schematic into our design, we could not access upper 128MB of memory when using the GEL file--otherwise it was OK. Tough to find and fix.

Please incorporate this change into the master AM3359 ICE gel file.

http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/791/t/226939.aspx

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