Hi,
I'm working with the PDK 1.1.1.4 on a C6670 with CCS 5.2.
I decided to track all cache instructions and wrote asserts for the size and the block alignment of a cache request.
I did this because the doxygen documentation of CACHE_[inv/wb]L1d tells me:
To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size
I noticed that cache requests from CPPI and QMSS LLD are not aligned to the cache line size. The test is done in the OSAL functions Osal_qmssBeginMemAccess(void *ptr, uint32_t size) and Osal_cppiBeginMemAccess(void *ptr, uint32_t size). (Osal_qmssMalloc and Osal_cppiMalloc are written to return cache aligned memory)
So my questions are:
1. How do I generate a valid cache Instruction from the parameters Osal_qmssBeginMemAccess and Osal_qmssBeginMemAccess provide?
2. Is it save to adjust the address to the address of the next lower cache line?
Thanks,
Sebastian