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Cache alignment in qmss and cppi LLD

Hi,

I'm working with the PDK 1.1.1.4 on a C6670 with CCS 5.2.

I decided to track all cache instructions and wrote asserts for the size and the block alignment of a cache request.
I did this because the doxygen documentation of CACHE_[inv/wb]L1d tells me:

To prevent unintended behavior "blockPtr" should be aligned on the cache line size and "byteCnt" should be a multiple of the cache line size

I noticed that cache requests from CPPI and QMSS LLD are not aligned to the cache line size. The test is done in the OSAL functions  Osal_qmssBeginMemAccess(void *ptr, uint32_t size) and Osal_cppiBeginMemAccess(void *ptr, uint32_t size). (Osal_qmssMalloc and Osal_cppiMalloc are written to return cache aligned memory)

So my questions are:

1. How do I generate a valid cache Instruction from the parameters  Osal_qmssBeginMemAccess and  Osal_qmssBeginMemAccess provide?

2. Is it save to adjust the address to the address of the next lower cache line?

Thanks,

Sebastian

  • The "unintended" behavior is called false sharing.  Without other special precautions, performing cache operations on part of a line will affect the rest of the same line.  If an invalidate is performed, this could throw away unintended data.

    The LLDs can use a different technique for protecting from false sharing.  They grab a semaphore for the entire line (or much larger block of memory) such that only one core can have one of those lines in the cache.  Thus unaligned accesses are harmless.  Thus you don't have to do anything to the addresses generated by the LLD as they are not incorrect.

    However, if you want to keep your assert, you can "round down" the address and "round up" the size.  Assuming you are using DDR where cache lines are 128 bytes, you do the following:

    Lets say we want to invalidate 0x800000F8, length = 0x10.  You could round down the address to 0x80000080, and round up the size to 0x100 (two lines).

    If you had 0x800000E0, length 0x10 you would round address to 0x80000080 and size to 0x80 (one line).

    This equally applies to inv, wb, and wbinv.