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About XIP boot operation during 1st XIP_MUX2 mode on AM335x.

RY9983
Guru 10570 points
Other Parts Discussed in Thread: AM3359

Hello.

I have refered TRM 26.1.7.2.2 Pins Used (spruh73f: P4264).
It is described that :
  "The pins that are not listed below are not configured by the ROM code and are left at power-on defaults."

When I use SYSBOOT[4:0] = 11010b, the boot operation is below:
1st XIP_MUX2 --> 2nd UART0 --> 3rd SPI0 --> 4th MMC0

Can I think that it keeps default state on A12-A27 during 1st XIP_MUX2?
In other words, can I boot from XIP without isolate mechanism when I chose XIP_MUX2 as 1st boot?

Best regards,
RY 

  • 0
    TI__Guru**** 393215 points
    Hi RY,
     
    You should check the AM335X datasheet Table 2-7, columns "Ball Reset Release State" and "Reset Release Mode" for the signals that concern you (A12 - A27). They should be left low after reset for proper XIP booting.
  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points

    Biser.

    Thank you for your response.

    Biser Gatchev-XID said:

    You should check the AM335X datasheet Table 2-7, columns "Ball Reset Release State" and "Reset Release Mode" for the signals that concern you (A12 - A27). They should be left low after reset for proper XIP booting.

    Thanks, I checked Table 2-7 of datasheet.
    Is there no case of no needed of isolation?

    Since I am gonna use #32 set of GPMC configuration,
    the configuration of A12-A15 are Z and gpio mode at reset release.
    the configuration of A16-A27 are L and gpio mode at reset release.

    Further, I would like to connect only NOR Flash to GPMC.
    And, will not connect any other to UART0, SPI0 and MMC0.

    On TRM, It is described that :
      "The pins that are not listed below are not configured by the ROM code and are left at power-on defaults."

    So, If reset release state is kept during 1st XIP booting, it seems to no requirement of isolation for XIP booting.
    How do you think about this?

    Best regards,
    RY

  • 0 in reply to RY9983
    TI__Guru**** 393215 points
    Hi RY,
     
    Can you tell me exactly what type of NOR Flash you want to connect to GPMC? What is Data width, how many Address lines, are you going to use Address/Data multiplexed mode?
  • 0 in reply to Biser Gatchev-XID
    Prodigy 45 points

    Hi Biser,

    Can you tell me what's the function with the pin of  VPP,  I connect the vpp pin to the 1.1v with core voltage together, the pins of VDDSH5 have 4.7V voltage output, I don,t know why, Do do you think the voltage outout from VDDSH5 pins because of this??  I had change 4 PCS am3359  on 4 boards,both of them had not connect the VPP pin to 1.1v, there is just one board change to OK , the vpp PIN don't have voltage output, the other threes board still have voltage output.I don't know why? can you help me?/

    The other question is that, the board which IS ok , the vpp PIN don't have voltage output, and the all voltage from tps65910aa1 is correct.  but the SYS conn't work,  we can't configura the PINS,  when it start  kernol,  THE boot will reset. do you knoe why??

     

  • 0 in reply to Jeson Lee
    TI__Guru**** 393215 points
    Hi Jason,
     
    First of all your problem has nothing in common with this thread. In the future please post your questions on new threads.
     
    Toa nswer your question: VPP is a power supply input, which should be left unconnected. VDDSH5 pins are also power supply inputs, which should be supplied either from 1.8V or 3.3V. To see 4.7V on these pins means you have a serious problem with your board power supply, and changing the processor will not help. If you want we can do a schematic and/or layout review of your design. You can request a review through your local TI FAE/representative.
  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points

    Hello, Biser.

    Thank you so much for helping me.
    Sorry, can I change the question to the simple one?

    I need to be left low after reset for proper XIP booting.
    However, the AM335x's GPMC port become "Ball Reset Release State" and "Reset Release Mode" immediately after reset release.
    After that, the pins need to be left low for any happening during ROM operation.

    Is it correct ?

    Best regards,
    RY

  • 0 in reply to RY9983
    TI__Guru**** 393215 points
    Hi RY,
     
    "Ball Reset Release State" and "Reset Release Mode" refer to all processor signal pins, not only GPMC. Yes, this is their default state and mode. Next, when ROM code starts it sets only the necessary pins, according to SYSBOOT settings. In your case, if on of the XIP boot modes is selected, this will be the pins listed in TRM Table 26-9. Please note that the pin names in this table are the "Mode 0" names. All other pins will remain in their Reset Release State/Mode until the u-boot starts and goes through pinmux configuration.
  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points

    Biser.

    Biser Gatchev-XID said:
    Please note that the pin names in this table are the "Mode 0" names. All other pins will remain in their Reset Release State/Mode until the u-boot starts and goes through pinmux configuration.

    Thank you for telling me important thing.

    Best regards,
    RY