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Having trouble setting McASP as slave

Yujia Wang
Prodigy 110 points

Hi all,

I am working on an audio project using AIC3106 and McASP.  I want AIC3106 to be in master mode and provide the clk for McASP to be slave.  I have set AIC3106 to output the bclk and wclk using

AIC3106_writeRegister(8, 0xC0);

and configured McASP as follows.  However, all I hear at the output is noise.  Could someone please help point out what I'm doing wrong?  Thanks!

MCASP->RMASK = 0xFFFFFFFF; 
MCASP->RFMT = 0x0001807C; 
MCASP->AFSRCTL = 0x00000110; 
MCASP->ACLKRCTL = 0x00000000;
MCASP->AHCLKRCTL = 0x00000000;
MCASP->RTDM = 0x00000003; 
MCASP->RINTCTL = 0x00000000;
MCASP->RCLKCHK = 0x00FF0000;

MCASP->PFUNC = 0;
MCASP->PDIR = 0x00000800;

  • 0
    TI__Guru* 84110 points

    Yujia,

    Which C67x DSP are you using?

    Once you configure the AIC3106, do the BCLK and WCLK look right at the pins?

    A good test method is to write a simple pattern into a buffer and send that buffer out the Tx port. Then you can look at the data pin also to confirm that the right pattern is going out as you expect.

    Then you can try sending data into the Rx port and look at the pins, then look at the data in the input buffer, and then loop that data back to the Tx side for an audible confirmation and/or look at the pins with your oscilloscope or logic analyzer.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 110 points

    Hi Randy,

    Thanks for the reply.  I am working with C6748 on the Logic PD board OMAP L138.  Basically I am trying to get to a sampling rate of 8 kHz.  Currently I believe this board provides a 24.56 MHz crystal oscillator that is tied to the mclk on aic3106, and ahclk on the mcasp?  While this can divide nicely to 8k on aic3106, on mcasp I think I can't divide it down low enough.  Should I just use the wclk as output then?  If so how would I configure the mcasp?  Also I am having a little trouble figuring out the pin configurations.        Really appreciate the help!

  • 0 in reply to Yujia Wang
    TI__Guru* 84110 points

    Yujia,

    The board comes with examples that include code for doing what you are trying to do. If you do not have those examples, you can visit the Logic PD website for downloads.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 110 points

    Hi Randy,

    Are you referring to the BSL files that Logic PD provided?  I did try their audio test file, but it is fixed at 48 kHz. 

  • 0 in reply to Yujia Wang
    TI__Guru* 84110 points

    Yujia,

    I will not be able to help you beyond this, but there may be others who can. My recommendation is that you mark this thread Answered and post a new thread with all the detail in the OMAP-L13x Forum. There you will find the best chance at finding someone with the right experience for you, and you may find someone has already asked a similar question, so be sure to search for some keywords for your question. Also, search on the TI Wiki Pages.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 110 points

    Randy,

    Thanks, will do.  But could you please differentiate between the bclk and mclk in aic3106?

  • 0 in reply to Yujia Wang
    TI__Guru* 84110 points

    Yujia,

    The direct answer is, no. To fully understand the AIC3106 clocks and usage, I would need to do the same as you and read its datasheet. That device is supported in a data converter forum and not this single core DSP forum. The C6748 datasheet and McASP User Guide show the pins and their timing relationships, then the AIC3106 document explains how it works, the board schematics show how the devices are connected (which you can assume is correct since it works for you at 48kHz), and there are examples that work at a different speed than you want.

    Usually, it is a simple case of changing dividers to get the new clock speed, but you have indicated that you are not able to divide down that low. That is surprising, but I assume that you have come to this conclusion from study and testing so I trust your conclusion.

    If you have it sampling at 48kHz, you can always duplicate your output samples to send the same value 6 times, or 1 time with 0's in between (if discrete theory and the on-board filters will work with it). For input, you can take 1 out of 6 samples and throw the others away. At least this way you can get your project running.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 110 points

    I will go ahead and ask this in the proper forum.  Thanks very much for the help and pointer.

    Best,

    Yujia