Cannot set EDMA3’s IER registers even when DRAEn enabled

Mukul,

I was able to set IER via shadow region registers and the intended interrupt worked. Though cannot say it for certain, I suspect the problem that I cannot see the update in IER registers in the memory view is due to some problem on the communiction between CCS and the core, and there were some inconsistencies between different runnings.

Paul

Mukul-san,
My customer encountered the same problem on AM1808EVM.
If you have any updates, could you let me know?
Best regards, RY

Hello RY

There were no significant updates from Paul on the root cause for the issue, additionally he was using a custom board.
I do not expect any issues with being able to set the EDMA registers in the shadow region or global region.

I would recommend checking the following

1) Make sure the clocks are enabled for CCs via gel file or some other entity. Simple check to see if the CC clocks are enabled is to check for the CC REVID register and make sure it shows a non-zero value

2) Make sure the MMU is not enabled when viewing registers in the memory window. If the AM1808 EVM is preloaded to boot from flash etc, it could've gone through uboot etc, and setup the MMU

3) If the issue is only with accessing the registers via memory window, I recommend checking accesses with simple programs, perhaps Starterware examples for EDMA will help.

Regards

Mukul

Mukul-san,

Thank you so much for your prompt reply.
I am gonna check your advice and will get back to you.
See you soon.

Best regards, RY

Mukul-san,
I am sorry for my late reply. I confirmed your check point.

1)
The EDMA_CC is enabled by gel.
I can see the 0x40019B00 in the REVID register.

2)
The MMU is disabled.
I checked CP15 register and I disabled with following code:

// MMU_Disable
asm(" MRC p15, #0, r1, c1, c0, #0 ");   // Read control register
asm(" TST  r0, #0x1 ");                // Is the MMU enabled?
asm(" BICNE r0, r0, #0x1 ");            // Clear bit[0] (Disable MMU)
asm(" MCRNE p15, #0, r1, c1, c0, #0 "); // Write control register and disable MMU

3)
I tried Starterware examples. But, issue is occured.

Although I tried all the advice from you, I can not see the update of IER register.
But, I can see the IER value when I read IER with CPU core.
So, it seems that the problem is by JTAG Emulation or CCS Memory view.

Do you have any idea to know root cause?

Best regards, RY

RY-san

Thanks for the update

Can you share the GEL file you are using for your starterware tests.

Yes I think it is likely a CCS/memory window setup issue, not a device issue.

Regards

Mukul

Mukul-san,

Thank you so much for your support !
I would like to attach the gel file.
I got it in the AM18x starterware v1.00.03.03.

7848.AM1808.gel

Best regards, RY

Hi RY-san

I did not see anything obviously wrong in the GEL file yet. However in your last email , the snapshot and the address you show for IER is incorrect, you are showing 0x01C0 0050 , instead of 0x01c0 1050. Your original post had the correct address.

Can you reconfirm that you are not looking at 0x01c0 0050 , as this address is reserved in the CC memory map.

Regards

Mukul

Mukul-san,

I could see the IER in the 0x01c0 0050.
Thanks a lot of your advise.

Best regards, RY