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Distinction between watchdog reset and power loss

Michał Kaszkiel
Prodigy 40 points
Other Parts Discussed in Thread: TMS320C6748

Hi!

I must devide resets on two groups: reset evoke by power loss and reset by watchdog. TMS320C6748 treats both of them in the same way. So, my question is about memory which keep data after watchdog reset and erase them after power loss. Does exist memory with that faetures? Save same tag in memory is the best way for me, because I want to know where my program terminated, too.

Thanks in advance.

Michael

  • 0
    TI__Guru* 84110 points

    Michael,

    You may need to go through your question or questions again. I have a lot of misunderstanding after this, what your question is.

    If you want to use non-volatile memory, those certainly exist and you can choose any that are compatible with the interfaces available on the C6748.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 40 points

    Thanks for your answer!

    I try to specify my problem. I need to check reset source. I want to detect resets generate by WDT. So, my idea is writing some tag in internal memory and read them after reset. Unfortunately, data saved in internal memory after reset sometimes change. Does exist memory which keep data after watchdog reset and erase them after power loss? Maybe can I detect WDT reset in other way?

    Regards,

    Michael

  • 0 in reply to Michał Kaszkiel
    TI__Guru* 84110 points

    Michael,

    Some of our C66x DSPs do have a mechanism to record the source of a reset, but this is not available in the C6748.

    According to the datasheet, the watchdog timer generates the same reset to the device as the PORz reset. The datasheet also says "Internal memory is not maintained through a POR", and POR includes the watchdog timer from the previous statement.

    There is no difference between the device state after a PORz pin has been asserted/deasserted and a watchdog timer reset. The only positive test would be to add logic external to the device that can detect or control the assertion of the PORz pin, and by elimination tell you that a watchdog reset may have occurred.

    If you have system features, such as PORz is only asserted when the power is cycled, then you could try memory tricks such as writing a pattern to memory and see if that pattern is retained. But I cannot say that any method like that would work reliably in production. As far as I can tell, the only reliable solution would have to use external logic of your design.

    Regards,
    RandyP