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C66 EMIF16 Routing

Wenjun Huang
Expert 1770 points

The C66 EMIF16 is clocking at CPU clk/6. Hence, if CPU clk is 1GHz, EMIF16 is clocking at 166.7MHz. With 16 data lines, the data transfer rate will be 2.67Gbps.

My question is I am using 2x devices to be connected to the C66 EMIF16 - FPGA, NAND flash. The address and data line will be bussed across both devices. As 166.7MHz is relatively high-speed, wouldn't the signal integrity (SI) be critical? If signal integrity is critical, having 2 parallel paths (to the 2 devices) from 1 line (eg. EMIFD00) will create a stub effect and degrade the SI.

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    TI__Mastermind 46460 points

    Wenjun,

    The EMIF16 is an asynchronous memory interface.  Even though the logic block is clocked by an internal CPU/6 clock, its transfer rate is not CPU/6.  I beleive the shortest possible cycle is three of these CPU/6 clock periods for a maximum transfer rate of about 55MHz.  The edge rates are still fast so proper signal conditioning of edge sensitive signals like CE and WE is stil recommended.  Depending on the board design these may even need buffering.  All inputs that latch data must be monotonic and not have excessive ringing.

    Tom