MCBSP FSX problem

mohammed alzain

hello,

I am using C6748, trying to send data through mcbsp port. I followed initialization procedure found in the (technical Ref manual) but I am a little bit confused about values of (SRGR) register, especially FWID & FPER.

I need to send data frame of 5 bytes at a time, on the oscilloscope CLKS1 is good, FSX1 looks good (pulse) but the output data is creepy.I set FPER to 64 and FWID to 40.

what are the proper values to these register fields.

here are the functions I used for initialization and data transmission and I hope some one will provide me with help

Fullscreen 1425.cslr_mcbsp.c Download

#include "mcbsp.h"
#include "main.h"
#include "evmc6748.h"
/*-------PINMUX-------*/
#define PINMUX_MCBSP1_REG       (1)
#define PINMUX_MCBSP1_MASK      (0x0F0F0F00)
#define PINMUX_MCBSP1_VAL       (0x02020200)


#define FPER_shift 16
#define CLKSM_shift 29
#define FSGM_shift 28
#define CLKGDV_shift 0
#define FWID_shift 8
#define XFRLEN1_shift 8
#define NULL 0

#define CLKSM_INTERNAL 1<<29
#define FSGM_DXR2XSR 0 << 28
#define FSGM_FSG 1 << 28

extern int i;

uint32_t MCBSP_init (McbspRegs *mcbsp, uint8_t CLKGDV,uint8_t FPER, uint8_t FWID, uint8_t xferlen)
{
	uint32_t rtn = ERR_INVALID_PARAMETER;
if (mcbsp==MCBSP1)
{
	EVMC6748_lpscTransition(PSC1, DOMAIN0, LPSC_MCBSP1, PSC_ENABLE);
	EVMC6748_pinmuxConfig( PINMUX_MCBSP1_REG,  PINMUX_MCBSP1_MASK,  PINMUX_MCBSP1_VAL);
	}

//reset mcbsp registers
mcbsp->SPCR=0;//hold Tx and Rx parts in reset
mcbsp->XCR=0;
mcbsp->SRGR=0;
mcbsp->PCR=0;
mcbsp->RCERE1=0;
mcbsp->XCERE1=0;
mcbsp->RCERE2=0;
mcbsp->XCERE2=0;
mcbsp->RCERE3=0;
mcbsp->XCERE3=0;

SETBIT(mcbsp->SRGR,(CLKGDV-1) <<CLKGDV_shift);
SETBIT(mcbsp->SRGR,(FPER-1) <<FPER_shift);
SETBIT(mcbsp->SRGR,(FWID-1) <<FWID_shift);
SETBIT(mcbsp->SRGR,MCBSP_SRGR_CLKSM);//internal input clock
SETBIT(mcbsp->SRGR,FSGM_FSG);

SETBIT(mcbsp->PCR,MCBSP_PCR_FSXP| MCBSP_PCR_CLKXM | MCBSP_PCR_FSXM);

SETBIT(mcbsp->XCR,XCR_XFIG_IGNORE |XCR_XDATDLY_1bit);//word length 8 bits |5 words in phase 1 | 1-bit data delay |Single-phase frame.

SETBIT(mcbsp->XCR,XCR_XFRLEN1_5word);
for (i=0; i<5; i++) {;}

SETBIT(mcbsp->SPCR,MCBSP_SPCR_GRST);// enable bit clk generator

for (i=0; i<20; i++) {;} // wait for GRST

SETBIT(mcbsp->SPCR,MCBSP_SPCR_XRST);// take Tx portion out of reset
for (i=0; i<5; i++) {;} //wait to check Transmit synchronization error

if (CHKBIT(mcbsp->SPCR,MCBSP_SPCR_XSYNCERR))// if XSYNCERR occured
	CLRBIT(mcbsp->SPCR,MCBSP_SPCR_XRST); // reset transmitter to clear the error

if (!CHKBIT(mcbsp->SPCR,MCBSP_SPCR_XRST))
SETBIT(mcbsp->SPCR,MCBSP_SPCR_XRST);// enable transmitter if it was reset by XSYNCERR

while (!CHKBIT(mcbsp->SPCR,MCBSP_SPCR_XRDY)) {;} //wait for XRDY
SETBIT(mcbsp->SPCR,MCBSP_SPCR_FRST);// enable frame sync generator


return (rtn);
}



uint32_t MCBSP_write(McbspRegs *mcbsp, int8_t *src_buffer, int16_t in_length)
{
   uint32_t rtn = ERR_INVALID_PARAMETER;

   if ((mcbsp != NULL) && (src_buffer != NULL))
   {
      uint32_t i;
      uint32_t mcbsp_DXR = mcbsp->DXR;
      
      // transmit data one byte at a time, copy receive data into input buffer.
      for (i = 0; i < in_length; i++)
      {
         // wait for tx buffer to be empty.
         if (CHKBIT (mcbsp->SPCR,MCBSP_SPCR_XRDY)){
           mcbsp_DXR=*src_buffer;
               src_buffer++;                  
         
         // copy the tmp reg to the real thing.
         mcbsp->DXR = mcbsp_DXR;
         }
         
         }
      
      rtn = ERR_NO_ERROR;
   }

   return (rtn);
}

thanks...

over 13 years ago

0 RandyP over 13 years ago

TI__Guru* 84110 points

Mohammed,

There are several other registers that must be set to get everything configured. You want to go through the documentation to see all the different registers and how they affect your operation.

For the registers you have mentioned, their effects are shown in the waveform in Figure 9. Programmable Frame Period and Width. You have programmed those and you are seeing valid results, from your description. You have not followed the recommendation just above that Figure with respect to the value of FWID.

There are several other sections, perhaps the whole McBSP User's Guide, that you also need to read and understand for setting up the rest of this communication channel. For example, Figure 11. Single-Phase Frame of Four 8-Bit Elements shows how the elements are presented within a frame. There are registers to set the size and count of these elements.

Regards,
RandyP

0 mohammed alzain over 13 years ago in reply to RandyP

Prodigy 215 points

hello RandyP,

RandyP said:

There are several other registers that must be set to get everything configured

- do you mean the receiver registers?? I am using one way transmission and I have no receiving side.

here is a modified code of the MCBSP_init() function.

Fullscreen 4520.mcbsp.c Download

#include "mcbsp.h"
#include "main.h"
#include "evmc6748.h"
/*-------PINMUX-------*/
#define PINMUX_MCBSP1_REG       (1)
#define PINMUX_MCBSP1_MASK      (0x0F0F0F00)
#define PINMUX_MCBSP1_VAL       (0x02020200)


#define FPER_shift 16
#define CLKSM_shift 29
#define FSGM_shift 28
#define CLKGDV_shift 0
#define FWID_shift 8
#define XFRLEN1_shift 8
#define NULL 0

#define CLKSM_INTERNAL 1<<29
#define FSGM_DXR2XSR 0 << 28
#define FSGM_FSG 1 << 28

extern int i;

uint32_t MCBSP_init (McbspRegs *mcbsp, uint8_t CLKGDV,uint8_t FPER, uint8_t FWID, uint8_t xferlen)
{
	uint32_t rtn = ERR_INVALID_PARAMETER;
if (mcbsp==MCBSP1)
{
	EVMC6748_lpscTransition(PSC1, DOMAIN0, LPSC_MCBSP1, PSC_ENABLE);
	EVMC6748_pinmuxConfig( PINMUX_MCBSP1_REG,  PINMUX_MCBSP1_MASK,  PINMUX_MCBSP1_VAL);
	}

//reset mcbsp registers
mcbsp->SPCR=0;//hold Tx and Rx parts in reset
mcbsp->XCR=0;
mcbsp->SRGR=0;
mcbsp->PCR=0;

mcbsp->MCR=0;

mcbsp->RCERE0=0;
mcbsp->RCERE1=0;
mcbsp->RCERE2=0;
mcbsp->RCERE3=0;

mcbsp->XCERE0=0;
mcbsp->XCERE1=0;
mcbsp->XCERE2=0;
mcbsp->XCERE3=0;


SETBIT(mcbsp->SRGR,
		(CLKGDV-1) <<CLKGDV_shift | //
		(FPER-1) <<FPER_shift | //
		(FWID-1) <<FWID_shift | //
		MCBSP_SRGR_CLKSM | //internal input clock
		FSGM_FSG | //
		MCBSP_SRGR_CLKSP); //Falling edge of CLKS generates CLKG and FSG.

SETBIT(mcbsp->PCR,MCBSP_PCR_FSXP| MCBSP_PCR_CLKXM | MCBSP_PCR_FSXM);

SETBIT(mcbsp->XCR,XCR_XFIG_IGNORE |XCR_XDATDLY_1bit);//word length 8 bits |5 words in phase 1 | 1-bit data delay |Single-phase frame.

SETBIT(mcbsp->XCR,XCR_XFRLEN1_5word);
for (i=0; i<5; i++) {;}

SETBIT(mcbsp->SPCR,MCBSP_SPCR_GRST);// enable bit clk generator

for (i=0; i<20; i++) {;} // wait for GRST

SETBIT(mcbsp->SPCR,MCBSP_SPCR_XRST);// take Tx portion out of reset
for (i=0; i<5; i++) {;} //wait to check Transmit synchronization error

if (CHKBIT(mcbsp->SPCR,MCBSP_SPCR_XSYNCERR))// if XSYNCERR occured
	CLRBIT(mcbsp->SPCR,MCBSP_SPCR_XRST); // reset transmitter to clear the error

if (!CHKBIT(mcbsp->SPCR,MCBSP_SPCR_XRST))
SETBIT(mcbsp->SPCR,MCBSP_SPCR_XRST);// enable transmitter if it was reset by XSYNCERR

while (!CHKBIT(mcbsp->SPCR,MCBSP_SPCR_XRDY)) {;} //wait for XRDY
SETBIT(mcbsp->SPCR,MCBSP_SPCR_FRST);// enable frame sync generator


return (rtn);
}



uint32_t MCBSP_write(McbspRegs *mcbsp, int8_t *src_buffer, int16_t in_length)
{
   uint32_t rtn = ERR_INVALID_PARAMETER;

   if ((mcbsp != NULL) && (src_buffer != NULL))
   {
      uint32_t i;
      uint32_t mcbsp_DXR = mcbsp->DXR;
      
      // transmit data one byte at a time, copy receive data into input buffer.
      for (i = 0; i < in_length; i++)
      {
         // wait for tx buffer to be empty.
         if (CHKBIT (mcbsp->SPCR,MCBSP_SPCR_XRDY)){
           mcbsp_DXR=*src_buffer;
               src_buffer++;                  
         
         // copy the tmp reg to the real thing.
         mcbsp->DXR = mcbsp_DXR;
         }
         
         }
      
      rtn = ERR_NO_ERROR;
   }

   return (rtn);
}

the problem I am facing is that, between frames and 1's(separated by 3 or more zeros ) there appears to be some sort of transitioning (like capacitor charge curve), which has a level of almost the data its self - which leads to receiver confusion.

the image above illustrates the problem clearly.

the yellow boxes shows the out put data - in this case it's 0xFF, the red box shawes the inactive frame period which must be at level zero.

how can I fix this????

0 RandyP over 13 years ago in reply to mohammed alzain

TI__Guru* 84110 points

Mohammed,

RandyP said:

There are several other registers that must be set to get everything configured

mohammed alzain said:
- do you mean the receiver registers?? I am using one way transmission and I have no receiving side.

You mentioned two fields of SRGR, FPER and FWID, to which I stated that there are other registers. You had not mentioned any other registers and had not followed our recommendation on one of those two fields. I apologize that my wording is unclear.

Your code does not use our CSL but apparently your own macros or functions. That will make it very difficult for someone to debug what you have done with those functions because they are unfamiliar and would have to be debugged in addition to your code. This is a good reason to start from a working example, such as found from the board vendor, the TI C6x1x Workshop, and the TI CSL (perhaps in the PSP, I am not sure). I recommend you find a working example to start from. This will save you a lot of time having to debug things that were already debugged when writing those examples.

Your waveforms with the three-stating data line would appear to be TDM responses to unused channels. When in TDM mode, a given McBSP port will only drive the data line when it is time for one of the channels that it owns. I doubt you meant to use TDM mode, so please check your register settings against the User Guide, searching especially for the keyword TDM.

Regards,
RandyP

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MCBSP FSX problem