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MIPI DSI in videomode problems

Ruud Siebierski
Prodigy 85 points
Other Parts Discussed in Thread: SYSCONFIG

Hi,

I'm trying to get a MIPI-DSI panel running in videomode. The panel already was running in command-mode using the taal-driver. Now we also want to get videomode working. The panel is 800x480 pixels.
The kernel I'm using is from the Linaro Android 12.04 build.

It seems like there is no VSYNC interrupt generated, but i don't know where to start looking.
From the minicom capture (also attached to the post):

OMAPFB: ioctl WAITFORVSYNC

and after a while:

OMAPFB: ioctl failed: -110

In the kernel config CONFIG_OMAP2_DSS_FAKE_VSYNC is enabled (is this wrong, i expected it only to be used when in manual update mode?)

Would really appreciate the help.

Regards,

Ruud 

4062.minicomcap.txt

  • 0
    TI__Intellectual 1035 points

    Hi Ruud

    Command-mode is actually less demanding from OMAP4 point of view, as the panel has it's own framebuffer and you don't need to concern too much about the DSI timings.

    Here are the things that come to mind, although it is not an exhaustive list.

    • You need to disable the stall mode on the display controller. DISPC_CONTROL[11]
    • You have to calculate the timings for DISPC and DSI based on the panel datasheet blankings and pixel clock.
    • Yes. You should disable CONFIG_OMAP2_DSS_FAKE_VSYNC, or DISPC and DSI will not be properly configured.

    The timing parameters are usually set on the board file, for example, for Blaze Tablet which has a video mode display, the timings are set on arch/arm/mach-omap2/board-44xx-tablet-panel.c

    Let me know how you do

    Regards

    Rafael

  • 0 in reply to Rafael Rodriguez
    Prodigy 85 points

    Hi Rafael,

    Thanks for your time+answer.

    I checked the stallmode and disabled the fake vsync in the kernel config. Furthermore i spent (quite) some time calculating the timing parameters using par 10.3.4.5.12 of the OMAP4460 TRM.

    Below is the output of cat /d/omapdss/clk

    At the moment i don't care about tearing effects, as long a i get some pixels on the display. I'll have to check with a scope tomorrow if any data is coming out of the interface.

    Best regards,

    Ruud

    - DSS -

    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
    - DISPC -
    dispc fclk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    fck 172193630
    - DISPC-CORE-CLK -
    lck 172193630 lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck 172193630 lck div 1
    pck 43048407 pck div 4
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck 42666666 lck div 4
    pck 42666666 pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint 2021052 regn 19
    CLKIN4DDR 860968152 regm 213
    DSI_PLL_HSDIV_DISPC (PLL1_CLK1) 172193630 regm_dispc 5 (on)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2) 172193630 regm_dsi 5 (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK 172193630
    DDR_CLK 215242038
    TxByteClkHS 53810509
    LP_CLK 8609681

  • 0 in reply to Ruud Siebierski
    Prodigy 85 points

    Hi,

    It seems now my previous problems are gone.

    When i look at the irq stats of the DISPC it looks promising;

    root@android:/ # root@android:/ # cat /d/omapdss/dispc_irq
    period 5992 ms
    irqs 251
    FRAMEDONE 0
    VSYNC 251
    EVSYNC_EVEN 0
    EVSYNC_ODD 0
    ACBIAS_COUNT_STAT 0
    PROG_LINE_NUM 239
    GFX_FIFO_UNDERFLOW 0
    GFX_END_WIN 251
    PAL_GAMMA_MASK 0
    OCP_ERR 0
    VID1_FIFO_UNDERFLOW 0
    VID1_END_WIN 251
    VID2_FIFO_UNDERFLOW 0
    VID2_END_WIN 0
    VID3_FIFO_UNDERFLOW 0
    VID3_END_WIN 0
    SYNC_LOST 0
    SYNC_LOST_DIGIT 0
    WAKEUP 0
    FRAMEDONE2 0
    VSYNC2 0
    ACBIAS_COUNT_STAT2 0
    SYNC_LOST2 0

    However, the packets seem to get stuck at DSI level. My intention was to configure 2 VCs, VC0 in command mode, for sending commands, VC1 in videomode for sending video data. As can be seen below, only packets over VC0 are sent. And i confirmed the figures below with a scope, i only saw the commands passing by, no pixel data at all.

    root@android:/ # cat /d/omapdss/dsi1_irqs
    period 147015 ms
    irqs 30
    -- DSI1 interrupts --
    VC0 30
    VC1 0
    VC2 0
    VC3 0
    WAKEUP 0
    RESYNC 0
    PLL_LOCK 3
    PLL_UNLOCK 2
    PLL_RECALL 0
    COMPLEXIO_ERR 0
    HS_TX_TIMEOUT 0
    LP_RX_TIMEOUT 0
    TE_TRIGGER 0
    ACK_TRIGGER 0
    SYNC_LOST 0
    LDO_POWER_GOOD 0
    TA_TIMEOUT 0
    -- VC interrupts --
    CS 0 0 0 0
    ECC_CORR 0 0 0 0
    PACKET_SENT 30 0 0 0
    FIFO_TX_OVF 0 0 0 0
    FIFO_RX_OVF 0 0 0 0
    BTA 30 0 0 0
    ECC_NO_CORR 0 0 0 0
    FIFO_TX_UDF 0 0 0 0
    PP_BUSY_CHANGE 0 0 0 0
    -- CIO interrupts --
    ERRSYNCESC1 0
    ERRSYNCESC2 0
    ERRSYNCESC3 0
    ERRESC1 0
    ERRESC2 0
    ERRESC3 0
    ERRCONTROL1 0
    ERRCONTROL2 0
    ERRCONTROL3 0
    STATEULPS1 0
    STATEULPS2 0
    STATEULPS3 0
    ERRCONTENTIONLP0_1 0
    ERRCONTENTIONLP1_1 0
    ERRCONTENTIONLP0_2 0
    ERRCONTENTIONLP1_2 0
    ERRCONTENTIONLP0_3 0
    ERRCONTENTIONLP1_3 0
    ULPSACTIVENOT_ALL0 0
    ULPSACTIVENOT_ALL1 0

    My DSI config is:

    root@android:/ # cat /d/omapdss/dsi1_regs
    DSI_REVISION 00000030
    DSI_SYSCONFIG 00000015
    DSI_SYSSTATUS 00000001
    DSI_IRQSTATUS 00000000
    DSI_IRQENABLE 0015c000
    DSI_CTRL 00faee99
    DSI_COMPLEXIO_CFG1 6a000321
    DSI_COMPLEXIO_IRQ_STATUS 00000000
    DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
    DSI_CLK_CTRL a034400a
    DSI_TIMING1 ffff7fff
    DSI_TIMING2 ffff7fff
    DSI_VM_TIMING1 17017017
    DSI_VM_TIMING2 04040404
    DSI_VM_TIMING3 01af0320
    DSI_CLK_TIMING 00001a11
    DSI_TX_FIFO_VC_SIZE 13121110
    DSI_RX_FIFO_VC_SIZE 13121110
    DSI_COMPLEXIO_CFG2 00030000
    DSI_RX_FIFO_VC_FULLNESS 00000000
    DSI_VM_TIMING4 00487296
    DSI_TX_FIFO_VC_EMPTINESS 1f1f1e1f
    DSI_VM_TIMING5 0082df3b
    DSI_VM_TIMING6 7a6731d1
    DSI_VM_TIMING7 0012000f
    DSI_STOPCLK_TIMING 00000080
    DSI_VC_CTRL(0) 20808f81
    DSI_VC_TE(0) 00000000
    DSI_VC_LONG_PACKET_HEADER(0) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
    DSI_VC_SHORT_PACKET_HEADER(0) 00000000
    DSI_VC_IRQSTATUS(0) 00000004
    DSI_VC_IRQENABLE(0) 000000db
    DSI_VC_CTRL(1) 20808fb3
    DSI_VC_TE(1) 00000000
    DSI_VC_LONG_PACKET_HEADER(1) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
    DSI_VC_SHORT_PACKET_HEADER(1) 00000000
    DSI_VC_IRQSTATUS(1) 00000000
    DSI_VC_IRQENABLE(1) 000000db
    DSI_VC_CTRL(2) 20808d81
    DSI_VC_TE(2) 00000000
    DSI_VC_LONG_PACKET_HEADER(2) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
    DSI_VC_SHORT_PACKET_HEADER(2) 00000000
    DSI_VC_IRQSTATUS(2) 00000000
    DSI_VC_IRQENABLE(2) 000000db
    DSI_VC_CTRL(3) 20808d81
    DSI_VC_TE(3) 00000000
    DSI_VC_LONG_PACKET_HEADER(3) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
    DSI_VC_SHORT_PACKET_HEADER(3) 00000000
    DSI_VC_IRQSTATUS(3) 00000000
    DSI_VC_IRQENABLE(3) 000000db
    DSI_DSIPHY_CFG0 12281220
    DSI_DSIPHY_CFG1 42060f38
    DSI_DSIPHY_CFG2 b800000e
    DSI_DSIPHY_CFG5 e7000000
    DSI_PLL_CONTROL 00000000
    DSI_PLL_STATUS 00000383
    DSI_PLL_GO 00000000
    DSI_PLL_CONFIGURATION1 1081aa25
    DSI_PLL_CONFIGURATION2 00656008

    The panel i'm using is 800x480x24, i used the lg4591 driver as a sort of reference.

    By the way, i saw some older post mentioning a OMAP Programming Manual F, is this an existing document? Because i can't find it anywhere.
    The TRM is actually very good, what i personally am missing is a good kernel OMAPDSS design.

    Best regards,

    Ruud Siebierski

  • 0 in reply to Ruud Siebierski
    TI__Intellectual 1035 points

    Hi Ruud

    I would like to check your timing calculations, just to rule out any problems there first. 

    Could you please share your DISPC and DSI parrameters? blankings, regm, regn, m4reg, m5reg, etc you calculated?

    I am not aware of an OMAP Programming Manual F. I will check.

    Thanks!!

    Rafael 

  • 0 in reply to Rafael Rodriguez
    Prodigy 85 points

    Hi Rafael,

    Thanks for looking into my problem!

    The display i'm using, as mentioned earlier is 800x480, hfp=hsw=hbp=32, vfp=vsw=vbp=4, 24bits pixels.
    Refresh rate about 60Hz, so 812x576pix x 60 x 24 = 673505280 bits/s, using 2 datalanes -> 336.7 Mbit/s/lane -> DDR clock = 168.376 MHz

    Fint about 2 MHz, sysclk = 38.4 MHz -> REGN = 19.2-1 = 18

    REGM = (18+1) x 673,505MHz / (2 x 38.4) = 167 (rounded up)

    Ftxbyteclkhs = Fclk4ddr / 16 = 673.505 / 16 = 42.09 MHz.

    R = 2/3 (according to table 10-495) -> Fvp_pclk = 28.063 MHz

    (M4REG+1) x LCD x PCD = 24 --> M4REG = 5, LCD = 1, PCD = 4, I set M5REG equal to M4REG, so M5REG = 5.

    I also tried with M4REG=M5REG=7, LCD=1, PCD=3.

    [ 13.738281] omapdss DISPC: dispc_restore_context
    [ 13.743164] omapdss DISPC: channel 0 xres 480 yres 800
    [ 13.748596] omapdss DISPC: pck 28062
    [ 13.752380] omapdss DISPC: hsw 32 hfp 32 hbp 32 vsw 4 vfp 4 vbp 4
    [ 13.758819] omapdss DISPC: hsync 48718Hz, vsync 59Hz
    [ 13.758819] omapdss DSI: PLL init
    [ 13.767547] omapdss DSI: PLL init done
    [ 13.771514] omapdss DSI: dsi_pll_set_clock_div()
    [ 13.771514] omapdss DSI: DSI Fint 2021052
    [ 13.780700] omapdss DSI: clkin (dss_sys_clk) rate 38400000, highfreq 0
    [ 13.787597] omapdss DSI: CLKIN4DDR = 2 * 167 / 19 * 38400000 / 1 = 675031368
    [ 13.787597] omapdss DSI: Data rate on 1 DSI lane 337 Mbps
    [ 13.795043] omapdss DSI: Clock lane freq 168757842 Hz
    [ 13.806060] omapdss DSI: regm_dispc = 5, DSI_PLL_HSDIV_DISPC (PLL1_CLK1) = 135006273
    [ 13.814239] omapdss DSI: regm_dsi = 5, DSI_PLL_HSDIV_DSI (PLL1_CLK2) = 135006273
    [ 13.822052] omapdss DSI: PLL config done
    [ 13.822174] omapdss DSI: PLL OK

    cat /d/omapdss/clk

    - DSS -
    dpll4_ck 1536000000
    DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
    - DISPC -
    dispc fclk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    fck 135006273
    - DISPC-CORE-CLK -
    lck 135006273 lck div 1
    - LCD1 -
    lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
    lck 135006273 lck div 1
    pck 33751568 pck div 4
    - LCD2 -
    lcd2_clk source = DSS_FCK (DSS_FCLK)
    lck 42666666 lck div 4
    pck 42666666 pck div 1
    - DSI1 PLL -
    dsi pll source = dss_sys_clk
    Fint 2021052 regn 19
    CLKIN4DDR 675031368 regm 167
    DSI_PLL_HSDIV_DISPC (PLL1_CLK1) 135006273 regm_dispc 5 (on)
    DSI_PLL_HSDIV_DSI (PLL1_CLK2) 135006273 regm_dsi 5 (on)
    - DSI1 -
    dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
    DSI_FCLK 135006273
    DDR_CLK 168757842
    TxByteClkHS 42189460
    LP_CLK 6750313

    root@android:/ # cat /d/omapdss/dsi1_regs

    DSI_REVISION 00000030
    DSI_SYSCONFIG 00000015
    DSI_SYSSTATUS 00000001
    DSI_IRQSTATUS 00000000
    DSI_IRQENABLE 0015c000
    DSI_CTRL 00faee98
    DSI_COMPLEXIO_CFG1 6a000321
    DSI_COMPLEXIO_IRQ_STATUS 00000000
    DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
    DSI_CLK_CTRL a034400a
    DSI_TIMING1 7fff7fff
    DSI_TIMING2 7fff7fff
    DSI_VM_TIMING1 17017017
    DSI_VM_TIMING2 04040404
    DSI_VM_TIMING3 01af0320
    DSI_CLK_TIMING 00001610
    DSI_TX_FIFO_VC_SIZE 13121110
    DSI_RX_FIFO_VC_SIZE 13121110
    DSI_COMPLEXIO_CFG2 00000000
    DSI_RX_FIFO_VC_FULLNESS 00000000
    DSI_VM_TIMING4 00487296
    DSI_TX_FIFO_VC_EMPTINESS 00000000
    DSI_VM_TIMING5 0082df3b
    DSI_VM_TIMING6 7a6731d1
    DSI_VM_TIMING7 0012000f
    DSI_STOPCLK_TIMING 00000080
    DSI_VC_CTRL(0) 20800f92
    DSI_VC_TE(0) 00000000
    DSI_VC_LONG_PACKET_HEADER(0) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
    DSI_VC_SHORT_PACKET_HEADER(0) 00000000
    DSI_VC_IRQSTATUS(0) 00000004
    DSI_VC_IRQENABLE(0) 000000db
    DSI_VC_CTRL(1) 20800f80
    DSI_VC_TE(1) 00000000
    DSI_VC_LONG_PACKET_HEADER(1) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
    DSI_VC_SHORT_PACKET_HEADER(1) 00000000
    DSI_VC_IRQSTATUS(1) 00000004
    DSI_VC_IRQENABLE(1) 000000db
    DSI_VC_CTRL(2) 20800d80
    DSI_VC_TE(2) 00000000
    DSI_VC_LONG_PACKET_HEADER(2) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
    DSI_VC_SHORT_PACKET_HEADER(2) 00000000
    DSI_VC_IRQSTATUS(2) 00000000
    DSI_VC_IRQENABLE(2) 000000db
    DSI_VC_CTRL(3) 20800d80
    DSI_VC_TE(3) 00000000
    DSI_VC_LONG_PACKET_HEADER(3) 00000000
    DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
    DSI_VC_SHORT_PACKET_HEADER(3) 00000000
    DSI_VC_IRQSTATUS(3) 00000000
    DSI_VC_IRQENABLE(3) 000000db
    DSI_DSIPHY_CFG0 0e201019
    DSI_DSIPHY_CFG1 42050d2c
    DSI_DSIPHY_CFG2 b800000b
    DSI_DSIPHY_CFG5 e7000000
    DSI_PLL_CONTROL 00000000
    DSI_PLL_STATUS 00000383
    DSI_PLL_GO 00000000
    DSI_PLL_CONFIGURATION1 10814e25
    DSI_PLL_CONFIGURATION2 00656008

    root@android:/ # cat /d/omapdss/dispc_irq
    DISPC_REVISION 00000040
    DISPC_SYSCONFIG 00002015
    DISPC_SYSSTATUS 00000001
    DISPC_IRQSTATUS 00000820
    DISPC_IRQENABLE 0016d64e
    DISPC_CONTROL 00018329
    DISPC_CONFIG 00020004
    DISPC_CAPABLE 00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
    DISPC_LINE_STATUS 00000063
    DISPC_LINE_NUMBER 00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD) 01f01f1f
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD) 00400403
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD) 00010004
    DISPC_GLOBAL_ALPHA ffffffff
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT) 00000000
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD) 031f01df
    DISPC_CONTROL2 00000000
    DISPC_CONFIG2 00000000
    DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2) 00040001
    DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_OVL_BA0(OMAP_DSS_GFX) 7f000000
    DISPC_OVL_BA1(OMAP_DSS_GFX) 7f000000
    DISPC_OVL_POSITION(OMAP_DSS_GFX) 00000000
    DISPC_OVL_SIZE(OMAP_DSS_GFX) 031f01df
    DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX) 12000099
    DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX) 04ff01d8
    DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX) 00000500
    DISPC_OVL_ROW_INC(OMAP_DSS_GFX) 00000001
    DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX) 00000001
    DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX) 00000000
    DISPC_OVL_TABLE_BA(OMAP_DSS_GFX) 00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD) 00000000
    DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2) 00000000
    DISPC_OVL_PRELOAD(OMAP_DSS_GFX) 000004ff
    DISPC_OVL_BA0(o) 7f177000
    DISPC_OVL_BA1(o) 7f177000
    DISPC_OVL_POSITION(o) 00000000
    DISPC_OVL_SIZE(o) 002f01df
    DISPC_OVL_ATTRIBUTES(o) 0600840d
    DISPC_OVL_FIFO_THRESHOLD(o) 07ff00e8
    DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
    DISPC_OVL_ROW_INC(o) 00000001
    DISPC_OVL_PIXEL_INC(o) 00000001
    DISPC_OVL_FIR(o) 04000400
    DISPC_OVL_PICTURE_SIZE(o) 002f01df
    DISPC_OVL_ACCU0(o) 00000000
    DISPC_OVL_ACCU1(o) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 264c26f4
    DISPC_OVL_FIR_COEF_H(o, i) 2f481ff2
    DISPC_OVL_FIR_COEF_H(o, i) 354916f0
    DISPC_OVL_FIR_COEF_H(o, i) 3b450ff0
    DISPC_OVL_FIR_COEF_H(o, i) 08404008
    DISPC_OVL_FIR_COEF_H(o, i) 0f453b01
    DISPC_OVL_FIR_COEF_H(o, i) 164935fc
    DISPC_OVL_FIR_COEF_H(o, i) 1f482ff7
    DISPC_OVL_FIR_COEF_HV(o, i) 243824f4
    DISPC_OVL_FIR_COEF_HV(o, i) 28391ff8
    DISPC_OVL_FIR_COEF_HV(o, i) 2d381bfc
    DISPC_OVL_FIR_COEF_HV(o, i) 32371701
    DISPC_OVL_FIR_COEF_HV(o, i) 123737f0
    DISPC_OVL_FIR_COEF_HV(o, i) 173732f0
    DISPC_OVL_FIR_COEF_HV(o, i) 1b382df0
    DISPC_OVL_FIR_COEF_HV(o, i) 1f3928f3
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 0000f4f4
    DISPC_OVL_FIR_COEF_V(o, i) 0000f8f2
    DISPC_OVL_FIR_COEF_V(o, i) 0000fcf0
    DISPC_OVL_FIR_COEF_V(o, i) 000001f0
    DISPC_OVL_FIR_COEF_V(o, i) 0000f008
    DISPC_OVL_FIR_COEF_V(o, i) 0000f001
    DISPC_OVL_FIR_COEF_V(o, i) 0000f0fc
    DISPC_OVL_FIR_COEF_V(o, i) 0000f3f7
    DISPC_OVL_BA0_UV(o) 00000000
    DISPC_OVL_BA1_UV(o) 00000000
    DISPC_OVL_FIR2(o) 04000400
    DISPC_OVL_ACCU2_0(o) 00000000
    DISPC_OVL_ACCU2_1(o) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_ATTRIBUTES2(o) 00000000
    DISPC_OVL_PRELOAD(o) 000007ff
    DISPC_OVL_BA0(o) 00000000
    DISPC_OVL_BA1(o) 00000000
    DISPC_OVL_POSITION(o) 00000000
    DISPC_OVL_SIZE(o) 00000000
    DISPC_OVL_ATTRIBUTES(o) 00008400
    DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
    DISPC_OVL_ROW_INC(o) 00000001
    DISPC_OVL_PIXEL_INC(o) 00000001
    DISPC_OVL_FIR(o) 04000400
    DISPC_OVL_PICTURE_SIZE(o) 00000000
    DISPC_OVL_ACCU0(o) 00000000
    DISPC_OVL_ACCU1(o) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_BA0_UV(o) 00000000
    DISPC_OVL_BA1_UV(o) 00000000
    DISPC_OVL_FIR2(o) 04000400
    DISPC_OVL_ACCU2_0(o) 00000000
    DISPC_OVL_ACCU2_1(o) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_ATTRIBUTES2(o) 00000000
    DISPC_OVL_PRELOAD(o) 00000100
    DISPC_OVL_BA0(o) 00000000
    DISPC_OVL_BA1(o) 00000000
    DISPC_OVL_POSITION(o) 00000000
    DISPC_OVL_SIZE(o) 00000000
    DISPC_OVL_ATTRIBUTES(o) 00008400
    DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
    DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
    DISPC_OVL_ROW_INC(o) 00000001
    DISPC_OVL_PIXEL_INC(o) 00000001
    DISPC_OVL_FIR(o) 04000400
    DISPC_OVL_PICTURE_SIZE(o) 00000000
    DISPC_OVL_ACCU0(o) 00000000
    DISPC_OVL_ACCU1(o) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_H(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_CONV_COEF(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_FIR_COEF_V(o, i) 00000000
    DISPC_OVL_BA0_UV(o) 00000000
    DISPC_OVL_BA1_UV(o) 00000000
    DISPC_OVL_FIR2(o) 04000400
    DISPC_OVL_ACCU2_0(o) 00000000
    DISPC_OVL_ACCU2_1(o) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_H2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_FIR_COEF_V2(o, i) 00000000
    DISPC_OVL_ATTRIBUTES2(o) 00000000
    DISPC_OVL_PRELOAD(o) 00000100

    Error from logging:

    [ 19.518524] omapdss DSI error: DSI error, irqstatus 400a0
    [ 19.524230] DSI IRQ: 0x400a0: RESYNC PLL_LOCK SYNC_LOST

    [ 31.443176] omapdss DSI error: DSI error, irqstatus 401a0
    [ 31.443206] DSI IRQ: 0x401a0: RESYNC PLL_LOCK PLL_UNLOCK SYNC_LOST

    The DSI_CTRL shows that the interface is disabled, although i don't see it being disabled in the software.

    Regards,

    Ruud

  • 0 in reply to Ruud Siebierski
    Prodigy 85 points

    Hi,

    I found an error in dsi.c where the dispc H-blanking timings were converted to dsi timing; always 4 datalanes were assumed.
    So the contents of DSI_VM_TIMING1 is : DSI_VM_TIMING1                      2f02f02f

    Still get the sync lost error by the way. Also stumbled upon the paragraph where is stated that the dsi interface is disabled when sync loss occurs, so that is clear.

    The programming manual was mentioned here: http://e2e.ti.com/support/omap/f/849/t/195366.aspx

    Best regards,

    Ruud

  • 0 in reply to Ruud Siebierski
    TI__Intellectual 1035 points

    Your calculations look great, they are a great job.
    Indeed the problem seems to be the DSI blankings.

    There are two sets of formulas to calculate them, one comes from the TRM:
    The values I got are:
    HFP_DSI=47
    HBP_DSI=92
    HSW_DSI=0
    TL=1344


    There are other empirical formulas used by some friends. The results are similar
    HFP_DSI=46
    HBP_DSI=93
    HSW_DSI=0
    TL=1344
    Those are register values.


    There is a patch, already merged, that uses the second formulas. It is here
    http://review.omapzoom.org/#/c/16063/

  • 0 in reply to Rafael Rodriguez
    Prodigy 85 points

    Hi,

    After applying the patch you suggested i didn't get SYNC_LOST errors and the DSI timing parameters look ok, as you suggested.

    The LCD display is still not working, but that seems a problem with the display, video data is coming out of the DSI interface, that was the main problem.

    So thanks!

    Ruud

  • 0 in reply to Ruud Siebierski
    Prodigy 40 points

    I like to continue the discussion of Ruud, who was hired for our company but recently left to be hired by another company.

    Display still is not working. Calculations from Ruud are OK.

    I have some concerns about the blanking calculations.

    Blanking settings for video source are defined in pixels and lines. Definitions come from a parallel video interface: think of one lane.

    These blanking settings have to be translated to bytes for the DSI interface where we can have a number of data lanes. in DSI the headers for the Synchronisation packets (VS Start, HS Start (these are the only blanking packets I found during measuring) all go over data lane 0 only. The positions of these blanking packets are very important since display timings depent on them.

    In calculating TL the Ratio R is used to calculate the number of bytes per lane, in our case TL=864 bytes.

    Same can be done for all blanking settings. In our case HFP=HSA=HBP=32pixels=48bytes and PPL=480pixels=720bytes.

    I think there are errors in your From Equation 3 calculation: You want to calculate the remaining bytes per lane available for horizontal blanking.

    I think it requires (WC+2) and not (WC+6) since you already accounted for the header 4 bytes and you want to account for the 2 bytes of CRC.

    In summary: it is unclear why the panel is not working. In current setting I measured HS Start packet and RGB888 packed pixel packet per line. I measured transition to LP11 state after HS Start packet. I did not measure any HS End packet, just going from LP11 state back to HS mode before sending the RGB888 packet.

    In another platform the display is working properly with same blanking settings (and a wide range around them). Difference is LP11 state. In this setup I have LP 11 state after the RGB888 packet and going back to HS mode for the sequence HFP HSA and HBP. How to achive this on your platform?

    Regards,

    Wim