DM8148, DSP McASP and EDMA3

Andrew Elder

Trying to track down a weird issue with McASP/EDMA code ported from a C674x project.

Hardware uses McASP0 with 2 Rx/Tx serializers talking I2S to a pair a stereo ADC/DACs.

Sample rate is 48 kHz and McASP generates and outputs frame sync at the correct rate.

The issue is that when I have EDMA3 CCNT set to 16 I get EDMA3 interrupts at a 6 kHz rate, but the correct rate is 48/16 = 3 kHz rate. This code worked correctly on a C6747. Are there differences in the McASP or EDMA cores embedded in the 814x SoC vs the C674x DSPs?

Thanks,

Andrew

over 12 years ago

0 Andrew Elder over 12 years ago

Expert 1680 points

What are "McASP0 CFG Support Registers" referenced in Table 2-6 "L4 Slow Peripheral Memory Map" of SPRS647C ?

I can't find them in the TRM - SPRUGZB ?

0 Andrew Elder over 12 years ago

Expert 1680 points

McASP FIFO registers are organized differently. How come no one in TI can reply promptly to this rather simple question?

0 TIguru over 12 years ago in reply to Andrew Elder

Expert 1430 points

TI Team,

Any help you can provide answering this question will be greatly appreciated.

0 Andrew Elder over 12 years ago in reply to TIguru

Expert 1680 points

I got this working. Did you have a specific question?

- Andrew

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DM8148, DSP McASP and EDMA3