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[DM8148] - McASP/Clock - Cannot Source External Clock Source

Other Parts Discussed in Thread: LM49450

Goal: Source an external 27.576 MHz Crystal connected to AUXOSC (OSC1) to McASP2

Issues: Cannot switch McASP2 clock source.

Background:
The DM8148 board using a LM49450 Stereo DAC with Class D AMP. It is a slave device
and requires MCLK, BCLK, WCLK, and Audio data to be sourced to it. I have an audio driver working
in with ALSA but the MCLK source from the DM8148 is configured to use the 20Mhz (OSC0) as the
high speed (AHCLKX) and the audio is distorted due to the 20Mhz MCLK.

The design has a  27.576MHz connected to the AUXOSC (OSC1) input on the DM8148. This clocked is
locked to the video source with the LM49450 MCLK set to 12.288Mhz and the data is 32 bit left justified.

Question:
Where can I find driver init code to change the source of the McASP clock source in the EZSDK?
Besides McASP_AHCLK_CLKSRC, are any other registers necessary to change the clock source?

Link to documentation:
DM8148 Technical Reference Manual: http://www.ti.com/lit/ug/sprugz8b/sprugz8b.pdf
Sections:
2.10.1.142 McASP_AHCLK_CLKSRC Register - Clock Source control register for McASP Master Clock (AH)
16.3.16 Receive Clock Control Register (ACLKRCTL)
16.3.17 Receive High-Frequency Clock Control Register (AHCLKRCTL)
16.3.28 Transmit Clock Control Register (ACLKXCTL)
16.3.29 Transmit High-Frequency Clock Control Register (AHCLKXCTL)
16.1.4 Functional Block Diagram - McASP Block Diagram
16.2.2.1 Transmit Clock - McASP Transmit Clock explanation
16.2.2.2 Receive Clock - McASP Receive Clock explanation

  • Hi Michael,

    We will check that and we will come back here soon. Sorry for the delay. Thank you.

    BR

    Vladimir

  • Hello,

    So you've changed the configuration for external 27.576 MHz crystal through AUXOSC to McASP2, but with sys fs entries you verify that in fact the clock is not changed. Is that correct?

    I personally also haven't tried this, but we will try to figure it out; I will involve someone here to help, if it is needed.

    I think that is the mcasp driver:

    <EZSDK_HOME>/board-support/linux-X.X/sound/soc/davinci/davinci-mcasp.c

    Can you please provide complete list of the registers, bit fields and their values that you've changed?

    Let me know. Thank you.

    BR

    Vladimir

  • Hi Michael,

    Also make sure that OSC_SRC[24] AUDIO_PLL_SOURCE bit is 0x1, thus selecting AUXOSC (OSC1) for source of the Audio PLL, and thus source for McASP modules.

    The McASP clock source can be selected in {EZSDK}/board-support/linux-2.6.37-psp04.04.00.01/arch/arm/mach-omap2/clock814x_data.c

    static const struct clksel osc_audio_dpll_mux_sel[] = {
        { .parent = &osc0_clkin_ck, .rates = div_1_0_rates },
        { .parent = &osc1_clkin_ck, .rates = div_1_1_rates },
        { .parent = NULL}
    };

    static struct clk osc1_clkin_ck = {
        .name        = "osc1_clkin_ck",
        .ops        = &clkops_null,
        .rate        = 22579000, /* Typically at 27M or 22.579MHz */
        .flags        = RATE_IN_TI814X | RATE_IN_DM385,
    };

    More information about how to change the clock source in Linux kernel and about the overall clock framework, you can find here:

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

    Regards,

    Pavel

  • Unfortunately,  that has not solved the issue.  Below are some addtional debug logs. I hope they help.
    I am unable to set sysclk20 as the source to
    mcasp2. The source still remans connected to sysclk22.

     

    ------------------- Audio Clock initialization ------------------------
    static int dvm_vmpp_audio_init(struct snd_soc_codec *codec)
    {
        struct clk *clkp_osc1, *clkp_audio_pll, *clkp_sysclk20, *clkp_mcasp2;
        struct dvm_vmpp_audio_priv *dvm_vmpp_audio = snd_soc_codec_get_drvdata(codec);
        int reg, ret;
        unsigned long clk_rate;

     

        clkp_osc1 = clk_get(NULL,"osc1_clkin_ck");
        clk_rate = clk_get_rate(clkp_osc1);
        printk(KERN_INFO "dvm_vmpp_audio_init: clock rate: %d\n", clk_rate) ;
        clk_set_rate(clkp_osc1, 24576000) ;

     

        clkp_audio_pll = clk_get(NULL,"audio_dpll_clkin_ck");   
        if(!clkp_audio_pll)
            printk("audio_dpll_clkin_ck\n");
        else
            printk("audio_dpll_clkin_ck success.\n");

     

        ret = clk_set_parent(clkp_audio_pll, clkp_osc1);
        printk(KERN_INFO "dvm_vmpp_audio_init: clk_set_parent(osc1) %d\n", ret) ;

      

        clkp_mcasp2 = clk_get(NULL,"davinci-mcasp.2");
        if(!clkp_mcasp2)
            printk("davinci-mcasp.2\n");
        else
            printk("davinci-mcasp.2 success.\n");

     

        clkp_sysclk20 = clk_get(NULL,"sysclk20_ck");
        if(!clkp_sysclk20)
            printk("sysclk20_ck\n");
        else
            printk("sysclk20_ck success.\n");

     

        ret = clk_set_parent(clkp_mcasp2, clkp_sysclk20);
        printk(KERN_INFO "dvm_vmpp_audio_init: clk_set_parent(clkp_sysclk20) %d\n", ret) ;

     

        clk_put(clkp_mcasp2) ;
        clk_put(clkp_osc1) ;
        clk_put(clkp_audio_pll) ;

     

    }

      

    ------------------ Console Output ------------------------------------

     

    dm814x-dvm login: dvm_vmpp_audio_init: clock rate: 24576000
    audio_dpll_clkin_ck success.
    dvm_vmpp_audio_init: clk_set_parent(osc1) 0
    davinci-mcasp.2 success.
    sysclk20_ck success.
    dvm_vmpp_audio_init: clk_set_parent(clkp_sysclk20) -22

     

    dvm_vmpp_audio_probe
    dvm_snd_soc_read: reg: 24
    asoc: dvm-audio-dai <-> davinci-mcasp.2 mapping ok

     

    --------------------- /sys/kernel/debug/clock -----------------------

     

    /sys/kernel/debug/clock/osc0_clkin_ck/sysclk22_ck/mcasp3_fck
    root@dm814x-dvm:/sys/kernel/debug/clock/osc0_clkin_ck/sysclk22_ck/mcasp3_fck# cat rate
    20000000

     

    root@dm814x-dvm:/sys/kernel/debug/clock/osc1_clkin_ck# ls
    audio_dpll_clkin_ck  flags                rate                 usecount
    root@dm814x-dvm:/sys/kernel/debug/clock/osc1_clkin_ck# cat rate
    24576000

     

    root@dm814x-dvm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck# ls
    audio_dpll_ck  flags          rate           usecount
    root@dm814x-dvm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck# cat rate
    24576000

     

    root@dm814x-dvm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck# ls
    audio_prcm1_out_ck  mcasp1_fck          rate
    flags               mcasp2_fck          usecount
    root@dm814x-dvm:/sys/kernel/debug/clock/osc1_clkin_ck/audio_dpll_clkin_ck/audio_dpll_ck/sysclk20_ck# cat rate
    307200000

     

    ------------------------------------------------------
  • Hi Michael,

    I can recall something similar I was investigating before. I found a workaround in u-boot. Please check here:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/197142/711664.aspx#711664

    Best Regards,

    Pavel