WEC7 Launch problem.

Jayaram,

Check the addrtab.inc or oemaddrtab.inc file for the static memory mapping for MMU. The syntax/interpretation has changed for wince 7. Check out the new syntax from some sample ce7 BSPs.

Hi Renjith,

Thanks for your reply.

I have checked addrtab_cfg.inc file in my BSP and compared with sample CE7 BSP(ti_evm_3530). The g_oalAddressTable syntax is same (Table format: cached address, physical address, size).

g_oalAddressTable

 IF BSP_SDRAM_BANK1_ENABLE <> 1
        DCD     0x84000000, 0x80000000, 128     ; SDRAM
        DCD     0x8C000000, 0x0C000000,  16     ; CS0, OneNand/Nand flash
        DCD     0x8D000000, 0x15000000,  16     ; CS5, LAN9115
        DCD     0x91000000, 0x48000000,  16     ; L4 Core/Wakeup registers
        DCD     0x92000000, 0x49000000,   1     ; L4 Peripheral
        DCD     0x93000000, 0x68000000,  16     ; L3 registers
        DCD     0x94000000, 0x6C000000,  16     ; SMS registers
        DCD     0x95000000, 0x6D000000,  16     ; SDRC registers
        DCD     0x96000000, 0x6E000000,  16     ; GPMC registers
        DCD     0x97000000, 0x40200000,   1     ; 62KB SRAM
        DCD     0x98000000, 0x5C000000,  16     ; L3 interconnect
        DCD     0x99000000, 0x00000000,   1     ; ROM
        DCD     0x00000000, 0x00000000,   0     ; end of table
 ELSE
        DCD     0x80100000, 0x80000000, 256     ;; SDRAM
        DCD     0x90100000, 0x90000000, 211     ; SDRAM
        
        DCD     0x9f800000, 0x0C000000,   1     ; CS0, OneNand/Nand flash
        DCD     0x9f900000, 0x15000000,   1     ; CS5, LAN9115
        DCD     0x9fa00000, 0x48000000,   4     ; L4 Core/Wakeup registers
        DCD     0x9fe00000, 0x49000000,   1     ; L4 Peripheral
        DCD     0x9ff00000, 0x68000000,   1     ; L3 registers
        
        DCD     0x9d400000, 0x6C000000,   1     ; SMS registers
        DCD     0x9d500000, 0x6D000000,   1     ; SDRC registers
        DCD     0x9d600000, 0x6E000000,  16     ; GPMC registers
        DCD     0x9e600000, 0x40200000,   1     ; 62KB SRAM
        DCD     0x9e700000, 0x5C000000,  16     ; L3 interconnect
        DCD     0x9f700000, 0x00000000,   1     ; ROM
        DCD     0x00000000, 0x00000000,   0     ; end of table


        
  ENDIF

Please help.

Thanks and regards,

Jayaram

Jayaram,

I have seen another platform where the definition is like this.

g_oalCE7DeviceTable
DCD 0x8F000000, 0x8F0000, 0x1000000, 0x00C00 ; 16MB uncached memory for device buffers
DCD 0x90000000, 0x480000, 0x0400000, 0x00C00 ; L4S
DCD 0x90400000, 0x4A0000, 0x0400000, 0x00C00 ; L4F
DCD 0x90800000, 0x44C000, 0x0400000, 0x00C00 ; L4WKUP
DCD 0x90C00000, 0x47C000, 0x0400000, 0x00C00 ; L4FW
DCD 0x91000000, 0x403000, 0x0100000, 0x00C00 ; OCMC RAM

Thank you for your response.

there is no uncashed memory.So OEMDEVICETABLE is not used.

Image still hangs.

Here is the full log:

Texas Instruments Windows CE NAND X-Loader for EVM 3730
Built Nov 21 2012 at 14:14:57
Version 6.15.00
..
Jumping to bootloader

Microsoft Windows CE Bootloader Common Library Version 1.4 Built Nov 21 2012 14:
12:14

Texas Instruments Windows CE EBOOT for Mistral OMAP EVM, Built Nov 21 2012 at 15
:04:54
EBOOT Version 1.1, BSP 6.15.00

TI DM3730 Version 0x2b89102f (unknown)
TPS659XX Version 0x30 (Unknown)
System ready!
Preparing for download...
INFO: Predownload....
Checking bootloader blocks are marked as reserved (Num = 14)

INFO: Boot configuration found
OALFlashStoreOpen: 4096 blocks, 64 sectors/block
OALFlashStoreOpen: 2048 bytes/sector, 14 reserved blocks
IsValidMBR: MBR sector = 0x380 (valid MBR)
OpenPartition: Partition Exists=0x1 for part 0x20.

>>> Forcing cold boot (non-persistent registry and other data will be wiped) <<<

Hit space to enter configuration menu 1...

Load NK image from flash memory
IsValidMBR: MBR sector = 0x380 (valid MBR)
OpenPartition: Partition Exists=0x1 for part 0x20.
BP_SetDataPointer at 0x0

ROMHDR (pTOC = 0x802f10a0) ---------------------
DLL First : 0x4001ef95
DLL Last : 0x4032f000
Physical First : 0x80101000
Physical Last : 0x80d146ac
Num Modules : 71
RAM Start : 0x88100000
RAM Free : 0x8810f000
RAM End : 0x9d400000
Num Copy Entries : 2
Copy Entries Offset : 0x806a7d78
Prof Symbol Length : 0x00000000
Prof Symbol Offset : 0x00000000
Num Files : 55
Kernel Flags : 0x00000000
FileSys RAM Percent : 0x80808080
Driver Glob Start : 0x00000000
Driver Glob Length : 0x00000000
CPU : 0x01c2
MiscFlags : 0x0002
Extensions : 0x80102020
Tracking Mem Start : 0x00000000
Tracking Mem Length : 0x00000000
------------------------------------------------

NK Image Loaded

Launch Windows CE image by jumping to 0x80001000...

Please help.....

Jayaram,

Jayaram K S said:

there is no uncashed memory.So OEMDEVICETABLE is not used.

I didn't understand what you meant here. Also can you confirm the oem address table config?

Hi Renjith,

About OEMDEvicetable :http://msdn.microsoft.com/en-us/library/gg155720.aspx

oem address table configuration in Microsoft provided BSP of TI_EVM_3530(WEC7).

g_oalAddressTable

IF BSP_SDRAM_BANK1_ENABLE <> 1
DCD 0x84000000, 0x80000000, 128 ; SDRAM
DCD 0x8C000000, 0x0C000000, 16 ; CS0, OneNand/Nand flash
DCD 0x8D000000, 0x15000000, 16 ; CS5, LAN9115
DCD 0x91000000, 0x48000000, 16 ; L4 Core/Wakeup registers
DCD 0x92000000, 0x49000000, 1 ; L4 Peripheral
DCD 0x93000000, 0x68000000, 16 ; L3 registers
DCD 0x94000000, 0x6C000000, 16 ; SMS registers
DCD 0x95000000, 0x6D000000, 16 ; SDRC registers
DCD 0x96000000, 0x6E000000, 16 ; GPMC registers
DCD 0x97000000, 0x40200000, 1 ; 62KB SRAM
DCD 0x98000000, 0x5C000000, 16 ; L3 interconnect
DCD 0x00000000, 0x00000000, 0 ; end of table
ELSE
DCD 0x84000000, 0x80000000, 128 ; SDRAM
DCD 0x8C000000, 0xA0000000, 128 ; SDRAM
DCD 0x94000000, 0x0C000000, 16 ; CS0, OneNand/Nand flash
DCD 0x95000000, 0x15000000, 16 ; CS5, LAN9115
DCD 0x96000000, 0x48000000, 16 ; L4 Core/Wakeup registers
DCD 0x97000000, 0x49000000, 1 ; L4 Peripheral
DCD 0x97100000, 0x68000000, 16 ; L3 registers
DCD 0x98100000, 0x6C000000, 16 ; SMS registers
DCD 0x99100000, 0x6D000000, 16 ; SDRC registers
DCD 0x9a100000, 0x6E000000, 16 ; GPMC registers
DCD 0x9b100000, 0x40200000, 1 ; 62KB SRAM
DCD 0x9b200000, 0x5C000000, 16 ; L3 interconnect
DCD 0x00000000, 0x00000000, 0 ; end of table
ENDIF

It is similar to the one that I am using...

Thanks..

Jayaram,

I'm not sure about 3530 BSP. But if you look into the documentation that you've sent, you can see that each entry has four fields. In your case this doesn't match.

struct _DeviceTableEntry {
    DWORD VirtualAddress;
    DWORD ShiftedPhysicalAddress;
    DWORD Size;
    DWORD Attributes;
}

Hi Renjith,

Sorry if i misled you.

OEMDeviceTable is not required (except on CPUs with ARMv7 architecture where it is required for mapping uncached devices), unless you want to provide additional kernel virtual address space. So I have not used OEMDeviceTable.

OEMAddressTable is used.   (http://msdn.microsoft.com/en-us/library/ee478351.aspx)

typedef struct {
    UINT32 CA;
    UINT32 PA;
    UINT32 size;
} OAL_ADDRESS_TABLE, *POAL_ADDRESS_TABLE;

Thanks...

Jayaram,

You are using an ARMv7 CPU. ARM Cortex-A8 is an ARMv7 CPU. I've not checked the ARMV7 startup code where it creates the static address table. If table selected based on the compiler flag or a macro then most likely it expected device table instead of OEMAddress table. Since there is no such parameter in the table to tell whether its using ARMv7 or not, it will naturally go by the compiler flag.