Am335x - CLKOUT2 value set

Veerapandian Murugesan1

Other Parts Discussed in Thread: TLV320AIC3104

Hi,

I am using the AM335x processor for my customized board. Audio codec also the part of my board. As per the AM335x EVM audio codec getting the 12 MHz in different way. But in my board just i need same 12Mhz from CLKOUT2. So i want to access some register for clkout2. So i saw one header file "arch/arm/mach-omap2/cm33xx.h" in the kernel code of Sitra.

is that a correct file for access the AM335x processor?

Table 8-161. CM_CLKOUT_CTRL Register:

As per the CM_CLKOUT_CTRL Register, Just i added some code with in a clkout2_enable fucniton.

static void __init clkout2_enable(void)
{
        struct clk *ck_32;
        int cm_clkout_ctrl_value;

        ck_32 = clk_get(NULL, "clkout2_ck");
        if (IS_ERR(ck_32)) {
                pr_err("Cannot clk_get ck_32\n");
                return;
        }

        clk_enable(ck_32);

        setup_pin_mux(clkout2_pin_mux);
//**************************************************************************
        cm_clkout_ctrl_value = readl(AM33XX_CM_CLKOUT_CTRL);
        cm_clkout_ctrl_value |= 0x000000B9; //---------------------------------------------------------> Example value
        writel(cm_clkout_ctrl_value, AM33XX_CM_CLKOUT_CTRL);

//**************************************************************************
}

Is that above three lines is enough to set the some frequency in CLKOUT2? are we need any other lines.

BIT 7:

This bit controls the external clock activity
0x0 = DIS : SYS_CLKOUT2 is disabled
0x1 = EN : SYS_CLKOUT2 is enabled ============> enable

BIT 5-3:

THis field controls the external clock divison factor
0x0 = DIV1 : SYS_CLKOUT2/1
0x1 = DIV2 : SYS_CLKOUT2/2
0x2 = DIV3 : SYS_CLKOUT2/3
0x3 = DIV4 : SYS_CLKOUT2/4
0x4 = DIV5 : SYS_CLKOUT2/5
0x5 = DIV6 : SYS_CLKOUT2/6
0x6 = DIV7 : SYS_CLKOUT2/7 ======================> may i use this value?
0x7 = DIV8 : SYS_CLKOUT2/8

BIT 2-0: CLKOUT2SOURCE

This field selects the external output clock source
0x0 = SEL0 : Select 32KHz Oscillator O/P
0x1 = SEL1 : Select L3 Clock
0x2 = SEL2 : Select DDR PHY Clock
0x3 = SEL4 : Select 192Mhz clock from PER PLL
0x4 = SEL5 : Select LCD Pixel Clock =========================> may i use this value?

I need 12MHz in the CLKOUT2? can you help me to get this value from AM335x processor.

Thanks,

Veera

over 13 years ago

0 peaves over 13 years ago

TI__Guru 64655 points

We plan to add the following paragraph to the next revision of the AM335x data sheet.

The AM335x CLKOUT1 and CLKOUT2 clock outputs should not be used as a synchronous clock for any of the peripheral interfaces because they were not timing closed to any other signals. These clock outputs also were not designed to source any time critical external circuits that require a low jitter reference clock. The jitter performance of these outputs is unpredictable due to complex combinations of many system variables. For example, CLKOUT2 may be sourced from several PLLs with each PLL supporting many configurations that yield different jitter performance. There are also other unpredictable contributors to jitter performance like application specific noise or crosstalk into the clock circuits. Therefore, there are no plans to specify jitter performance for these outputs.

You may not be able to use CLKOUT2 to source the audio codec clock because of the reasons described above.

Regards,
Paul

0 Jithin Shyam over 13 years ago in reply to peaves

Intellectual 485 points

Dear Team,

I want to set the clkout to 19.567MHZ current the clkout is 32KHZ.

which parameter to chages to achive 19.567Mhz. i want to check the quality of the signal and then used in my application.

Regards

Shyam

0 Amon Wu over 11 years ago in reply to peaves

Intellectual 820 points

hi paul

maybe we met the similar question,

we find CLKOUT2 is 32.768KHz. as you said , we can not use this pin for TLV320AIC3104 codec?

actually, we connect A14 for clock ,but we find no clock output from this pin, and the settings as follows.

attachment is the schem of our device,

/*Module pin mux for mcasp0 ,wubin*/

static struct pinmux_config mcasp0_pin_mux[] = {

{"mcasp0_aclkx.mcasp0_aclkx", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
{"mcasp0_fsx.mcasp0_fsx", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
{"mcasp0_axr0.mcasp0_axr0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
{"mcasp0_axr1.mcasp0_axr1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
{"mcasp0_ahclkx.mcasp0_ahclkx", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, // Is this pin config here？ or any advice?
{NULL, 0},

};

0 Amon Wu over 11 years ago in reply to peaves

Intellectual 820 points

Hi Paul
if we may not use CLKOUT2 for codec,which we could use?
in TRM
22.3.5.1 Transmit Clock
The transmit bit clock, ACLKX, (Figure 22-17) may be either externally sourced from the ACLKX pin or
internally generated, as selected by the CLKXM bit. If internally generated (CLKXM = 1), the clock is
divided down by a programmable bit clock divider (CLKXDIV) from the transmit high-frequency master
clock (AHCLKX).

where is the code I could check ? and external AHCLKX is critical for this problem, I think, right?

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Am335x - CLKOUT2 value set