Hi,
I've been doing some development on the Zoom Development Kit with the C6748 SOM. We've recently got our own board based upon the C6748 and I'm now trying to modify the GEL file for the particular mDDR on our board. We are using the Issi_IS43LR16320B-6BLI mDDR module and I used the TI spreadsheet (from the link below), together with the datasheet to calculate the different register values :
http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x
The modified GEL function for the ssi_IS43LR16320B-6BLI mDDR module:
DEVICE_DDRConfig(unsigned int ddr_type, float freq)
{
unsigned int j;
unsigned int tmp_SDCR;
// Enable the Clock to EMIFDDR SDRAM
PSC1_LPSC_enable(PD0, LPSC_DDR);
// Begin VTP Calibration
VTPIO_CTL &= ~0x00000040; // Clear POWERDN
VTPIO_CTL &= ~0x00000080; // Clear LOCK
VTPIO_CTL |= 0x00002000; // Set CLKRZ in case it was cleared before (VTP looks for CLKRZ edge transition)
VTPIO_CTL &= ~0x00002000; // Clear CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction)
VTPIO_CTL |= 0x00002000; // Set CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction)
j = 0;
// Polling READY bit to see when VTP calibration is done
while((VTPIO_CTL & 0x00008000) == 0) {
if( j++ > VTP_TIMEOUT ) {
GEL_TextOut("\tVTP Ready timeout\n","Output",1,1,1);
break;
}
}
VTPIO_CTL |= 0x00000080; // Set LOCK bit for static calibration mode
VTPIO_CTL |= 0x00000040; // Set POWERDN bit to power down VTP module
// End VTP Calibration
VTPIO_CTL |= 0x00004000; // Set IOPWRDN to allow powerdown of input receivers when PWRDNEN is set
// **********************************************************************************************
// Setting based on the Issi_IS43LR16320B-6BLI
// Config DDR timings
DRPYC1R = (0x0 << 8) | // Reserved
(0x1 << 7) | // EXT_STRBEN
(0x1 << 6) | // PWRDNEN
(0x0 << 3) | // Reserved
(0x4 << 0); // RL
// DRPYC1R Value = 0x000000C4
// Settings that change depending on DDR2 or MDDR
if( ddr_type == DDR2 ) {
DDR_SLEW = 0x00000000; // Disable Pull Downs, Disable LVCMOS Rx
tmp_SDCR = (0x0 << 25) | // MSDRAMEN
(0x1 << 20); // DDR2EN
GEL_TextOut("\tUsing DDR2 settings\n","Output",1,1,1);
}
else if( ddr_type == MDDR ) {
DDR_SLEW = 0x00000030; // Enable Pull Downs, Enable LVCMOS Rx
tmp_SDCR = (0x1 << 25) | // MSDRAMEN
(0x0 << 20); // DDR2EN
GEL_TextOut("\tUsing mDDR settings\n","Output",1,1,1);
}
else {
DDR_SLEW = 0x00000030; // Enable Pull Downs, Enable LVCMOS Rx
tmp_SDCR = (0x1 << 25) | // MSDRAMEN
(0x0 << 20); // DDR2EN
GEL_TextOut("\tUnknown DDR Type! Using MDDR settings\n","Output",1,1,1);
}
EMIFDDR_SDCR |= 0x00800000; // Set BOOTUNLOCK
EMIFDDR_SDCR = tmp_SDCR | // Settings that change depending on DDR2 or MDDR
(EMIFDDR_SDCR & 0xF0000000) | // Reserved
(0x0 << 27) | // DDR2TERM1
(0x0 << 26) | // IBANK_POS
(0x0 << 24) | // DDRDRIVE1
(0x0 << 23) | // BOOTUNLOCK
(0x0 << 22) | // DDR2DDQS
(0x0 << 21) | // DDR2TERM0
(0x1 << 19) | // DDRDLL_DIS
(0x1 << 18) | // DDRDRIVE0
(0x1 << 17) | // DDREN
(0x1 << 16) | // SDRAMEN
(0x1 << 15) | // TIMUNLOCK
(0x1 << 14) | // NM
(0x0 << 12) | // Reserved
(0x3 << 9) | // CL
(0x0 << 7) | // Reserved
(0x2 << 4) | // IBANK
(0x0 << 3) | // Reserved
(0x2 << 0); // PAGESIZE
// mDDR SDCR Value = 0x02034622
if( ddr_type == MDDR ) {
EMIFDDR_SDCR2 = 0x00000000; // IBANK_POS set to 0 so this register does not apply
}
// Let float -> integer truncate handle minus 1; Safer to round up for timings
EMIFDDR_SDTIMR1 = (((unsigned int) (110.0 * freq / 1000)) << 25) | // tRFC
(((unsigned int) ( 18.0 * freq / 1000)) << 22) | // tRP
(((unsigned int) ( 18.0 * freq / 1000)) << 19) | // tRCD
(((unsigned int) ( 12.0 * freq / 1000)) << 16) | // tWR
(((unsigned int) ( 42.0 * freq / 1000)) << 11) | // tRAS
(((unsigned int) ( 60.0 * freq / 1000)) << 6) | // tRC
(((unsigned int) ( 12.0 * freq / 1000)) << 3) | // tRRD
(EMIFDDR_SDTIMR1 & 0x4) | // Reserved
((2 - 1) << 0); // tWTR
EMIFDDR_SDTIMR2 = (EMIFDDR_SDTIMR2 & 0x80000000) | // Reserved
(0xB << 27) | // tRASMAX
(0x3 << 25) | // tXP
(0x0 << 23) | // tODT (Not supported)
(((unsigned int) (200.0 * freq / 1000)) << 16) | // tXSNR (tXSR for mDDR)
(0xC7 << 8) | // tXSRD (tXSR for mDDR)
(0x0 << 5) | // tRTP
(0x0 << 0); // tCKE
// SDTIMR1 Value @ 147.456MHz = 0x20913209
// SDTIMR2 Value @ 147.456MHz = 0x5E1DC700
EMIFDDR_SDCR &= ~0x00008000; // Clear TIMUNLOCK
// Let float -> integer truncate handle RR round-down; Safer to round down for refresh rate
EMIFDDR_SDRCR = (0x1 << 31) | // LPMODEN (Required for LPSC SyncReset/Enable)
(0x1 << 30) | // MCLKSTOPEN (Required for LPSC SyncReset/Enable)
(0x0 << 24) | // Reserved
(0x0 << 23) | // SR_PD
(0x0 << 16) | // Reserved
(((unsigned int) (7.8 * freq)) << 0); // RR
// SyncReset the Clock to EMIFDDR SDRAM
PSC1_LPSC_SyncReset(PD0, LPSC_DDR);
// Enable the Clock to EMIFDDR SDRAM
PSC1_LPSC_enable(PD0, LPSC_DDR);
// Disable self-refresh
EMIFDDR_SDRCR &= ~0xC0000000;
// SDRCR Value @ 147.456MHz = 0x00000493
// Set PBBPR to a value lower than default to prevent blocking
EMIFDDR_PBBPR = 0x20;
}
The PLL are correctly setup to provide a 221.184MHz clock on SYSCLK3 to achieve a mDDR clock frequency of 147.456 MHz. Upon execution of the GEL file I get the following errors on the console:
C674X_0: Output: Target Connected.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Cleared.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Setup Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: KICK Unlocked.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PSC Enable Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PLL0 init done for Core:442MHz
C674X_0: Output: mDDR initialization is in progress....
C674X_0: Output: PLL1 init done for DDR:147MHz
C674X_0: Output: Using mDDR settings
C674X_0: Output: PSC1 Sync Reset Transition Timeout on Domain 0, LPSC 6
C674X_0: Output: PSC1 Sync Reset Verify Timeout on Domain 0, LPSC 6
C674X_0: Output: PSC1 Enable Transition Timeout on Domain 0, LPSC 6
C674X_0: Output: PSC1 Enable Verify Timeout on Domain 0, LPSC 6
C674X_0: Trouble Reading Memory Block at 0xb000000c on Page 0 of Length 0x4: (Error -1202 @ 0xB000000C) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 5.0.681.0)
C674X_0: GEL: Error while executing OnTargetConnect(): target access failed at (*((unsigned int *) (0xB0000000+0x0C))&=~(0xC0000000)) [C6748.gel:145] at DEVICE_DDRConfig(1, 147.456) [C6748.gel:416] at Set_mDDR_147MHz() [C6748.gel:424] at Core_442MHz_mDDR_147MHz() [C6748.gel:267] at OnTargetConnect() .
C674X_0: Trouble Reading Register CSR: (Error -1202 @ 0x41) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 5.0.681.0)
C674X_0: Trouble Writing Memory Block at 0x1181b650 on Page 0 of Length 0x93d: (Error -1202 @ 0x64) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 5.0.681.0)
C674X_0: GEL: File: C:\Users\reinierc.RAPIDM\workspace_v5_2\gpio_example\Debug\gpio_example.out: Load failed.
Can anyone please advise me on what I'm doing wrong here?
Regards
Reinier