Hello,
Please help!!
We see glitches on the read and write access to the DDR3. We are using a
DDR3 SODIMM module.
With our Rev 0 (we begin our counting in proper fashion here, from 0 and not
1) board we felt our issue may have been crosstalk.
So for our Rev 1 board we added extra power/gnd planes to shield the DDR3 signal layers; we added 18+ mils of separation between DDR3 traces; and we moved everything that was not DDR3 related completely away from the DDR3 area on the PCB. Essentially we followed TI's guidelines.
We obtained almost the exact same results with the Rev 1 board as we did the Rev 0 board.
We noticed in some of TI's documentation for the C6678/Keystone devices they talk about the use of UDIMMs and then in another document they say the address/ctl lines cannot exceed 4.5" (or thereabouts). And the DDR3 UDIMM alone will exceed that! But what are we to make of the docs that talk about how to connect a DDR3 UDIMM? So for Rev 2 we are dumping the SODIMM module and going to go with discrete DDR3 SDRAMs.
But other than that, we don't know what else to do at this point.
From Rev 0 on, every other component on the PCB has worked, ethernet, I2C, PCIe, etc. And we have done many DDR and DDR2 layouts in the past.
Thanks so much!
